1,720,988 research outputs found
A design and verification methodology for networked embedded systems
No full textOggigiorno i Sistemi Dedicati di Rete (Networked Embeddedd Systems – NES) sono una tecnologia pervasiva. Il loro utilizzo comprende applicazioni per il monitoraggio, per l’automazione delle case, e per compiti in ambienti critici. La loro crescente complessità richiede nuove metodologie per poter effettuare efficientemente le fasi di progettazione e verifica.
Questo lavoro presenta un flusso di sviluppo generico per NES, supportato dall’implementazione di programmi per la loro applicazione. Il flusso di sviluppo sfrutta il linguaggio SystemC, e considera la rete come una dimensione dello spazio di progetto.
La metodologia di base comprende estensioni per considerare anche i casi in cui il NES sia implementato usando un middleware o in cui siano presenti dei requisiti di affidabilità.
Inoltre, sono stati implementati dei programmmi di traduzione per consentire l’adozione della metodologia proposta con design scritti in altri linguaggi per la descrizione dell'hardware.Nowadays, Networked Embedded Systems (NES’s) are a pervasive technology. Their use ranges from communication, to home automation, to safety critical fields. Their increasing complexity requires new methodologies for efficient design and verification phases.
This work presents a generic design flow for NES’s, supported by the implementation of tools for its application. The design flow exploits the SystemC language, and considers the network as a design space dimension. Some extensions to the base methodology have been performed to consider the presence of a middleware as well as dependability requirements.
Translation tools have been implemented to allow the adoption of the proposed methodology with designs written in other HW description languages
SystemC Simulation of Networked Embedded Systems
No full textThe design and simulation of next-generation networked embedded systems are a challenging task since System design choices may affect the network behavior and Network design choices may impact on the System design. For this reason, it is important —at the early stages of the design flow— to model and simulate not only the system under design, but also the heterogeneous networked environment in which it operates. However, System designers are more focused on System design issues and tools while Network aspects are dealt implicitly by choosing traditional protocols even if, in this case, the chance of joint optimization is lost. To solve this issue, we have exploited a modeling language traditionally used for System design —SystemC— to build a System/Network simulator named SystemC Network Simulation Library (SCNSL). This library allows to model network scenarios in which different kinds of nodes, or nodes described at different abstraction levels, interact together. The use of SystemC as unique tool has the advantage that HW, SW, and network can be jointly designed, validated and refined. As a case study, the proposed tool has been used to simulate a sensor network application and it
has been compared with NS-2, a well-known network simulator; SCNSL shows
nearly two-order-magnitude speed up with TLM modeling and about the same
performance as NS-2 with a mixed TLM/RTL scenario. The simulator is partially
available to the community at http://sourceforge.net/projects/scnsl/
Time-varying network fault model for the design of dependable networked embedded systems
No full textDependability is becoming a key design aspect of today networked embedded systems (NES's) due to their increasing application to safety-critical tasks. Dependability evaluation must be based on modelling and simulation of faulty application behaviors, which must be related to faulty NES behaviors under actual defects. However, NES's behave differently from traditional embedded systems when testing activities are performed on them. In particular, issues arise on the definition of correct behavior, on the best point to observe it, and on the temporal properties of the faults to be injected. The paper describes these issues, discusses some possible solutions and presents a new time-varying network-based fault model to represent failures in a more abstract and efficient way. Finally, the fault model has been used to support the design of a network-based control application where packet losses, end-to-end delay and signal distortion must be carefully controlled
Enabling tools for virtual platforms
No full textVirtual platforms are gaining attention for thedevelopment and validation of embedded softwarebefore the corresponding hardware is available.Transaction-level modelling (TLM) is the mostpromising technique to develop virtual platforms.However, modelling a complex system completelyat transaction level could be an expensive task. Thispaper presents recent developments done byEDALab to simplify the creation of TLM virtualplatforms. In particular, it describes 1) amethodology and a tool to generate TLM modelsfrom re-used IP cores described at register transferlevel (RTL) or by using model-driven design toolssuch as Matlab/Stateflow, 2) a SystemC/TLMlibrary to simulate packet-based communicationsoutside the system in case of networked embeddedsystems
Refinement of UML/MARTE models for the design of networked embedded systems
No full textNetwork design in distributed embedded applications is a novel challenging task which requires 1) the extraction of communication requirements from application specification and 2) the choice of channels and protocols connecting physical nodes. These issues are faced in the paper by adopting UML/MARTE as specification front-end and repository of refined versions of the model obtained by both simulation and analytical exploration of the design space. The emphasis is on using standard UML/MARTE elements for the description of networked embedded systems to allow re-use, tool interoperability and documentation generation. The approach is explained on a case study related to building automation
Network fault model for dependability assessment of networked embedded systems
No full textThis paper presents a network-based fault model for dependability assessment of distributed applications built over networked embedded systems. This fault model represents global failures in terms of wrong behavior of packet-based asynchronous data transmissions. Packets are subject to different faults, i.e., drop, cut, bit errors, and duplication; these events can model either HW/SW failures of the networked embedded systems or problems in the channel among them. The paper describes 1) the proposed fault model in relation with existing ones, 2) its possible application scenarios, and 3) a SystemC tool for the simulation of both fault-free and faulty wireless sensor networks. Experimental results show the validity of the approach in the verification of communication protocols and its support to determine the optimal number of nodes in a wireless sensor network based on the IEEE 802.15.4 standard. Part of the software is available at http://sourceforge.net/projects/scnsl/
Automatic Network Protocol Synthesis from UML Sequence Diagrams
No full textThis paper presents a methodology to automatically generate a simulable SystemC protocol implementation, starting from its specification given by using UML sequence diagrams. The methodology merges such diagrams into a single one, which is then used to generate the SystemC code. Two algorithms are used to show the merging and refining processes of these diagrams. SCNSL network simulator is exploited to simulate the generated code in a complete network scenario. As case study, the methodology is applied to sequence diagrams contained into IEEE 802.15.4 standard protocol specification
Automatic HDL Conversion and Abstraction Methodologies
No full textVirtual prototyping of embedded systems generally relies on the reuse of already developed components to sensibly reduce the time-to-market. However, in several cases, manual rewriting of legacy components is necessary because their existing descriptions cannot be easily integrated in the new design. This may be due either to the use of a different description language, e.g., SystemC instead of VHDL, or to the adoption of a different abstraction layer, e.g., Transaction Level Modeling (TLM) instead of Register Transfer Level (RTL). Several co-simulation techniques and tools have been proposed and commercialized to solve such a problem, but it requires the set up of a complex environment to manage the simulation of heterogeneous components. Moreover, these solutions cannot guarantee an efficient correct-by- evolution development process, where, for example, the alignment between RTL and TLM descriptions of the same component must be preserved during the initial design and the further evolution of the product.
In this context the paper presents the basic methodologies on which HIFSuite relies, a set of tools and APIs that allow system designers to automatize the reuse of existing components by providing conversion and abstraction capabilities, as well as easy development of custom tools for the automatic manipulation of HDL descriptions. In particular, HIFSuite allows to: (1) parse VHDL/Verilog RTL models; (2) extract an internal HIF representation; (3) manipulate the HIF representation through a set of powerful APIs; (4) abstract the HIF representation towards TLM; (5) generate an RTL or TLM 2.0 SystemC model which either reflects the changes introduced by steps 3 and/or 4, or it is functionally equivalent to the original VHDL/Verilog model
Automatic generation of self-adaptive transactors from PSL assertions
No full textThis paper presents an approach to automatically generate transactors that implement TLM protocols for RTL IPs, such that the RTL IPs can be abstracted towards corresponding TLM models and easily integrated inside a TLM virtual pro- totype. The obtained transactor is self-adaptive, since it allows plugging the target IP in the virtual prototype independently from the protocol implemented by the corresponding TLM initiator. The transactor is automatically created from the set of PSL assertions that describe the temporal behaviour of the communication protocol of the original RTL IP
Communication-aware design flow for dependable networked embedded systems
No full textThe paper presents a design methodology for distributed applications of networked embedded systems. The original contribution is the joint perspective on communication aspects and dependability. The methodology allows to model the dependability requirements of the application under design and the degree of dependability of involved components, like nodes, communication protocols, and channels. By assessing the dependability degree of a candidate solution, the methodology allows to iterate the synthesis process until requirements are met. The effectiveness of the proposed design flow is shown by an actual case study
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