1,720,955 research outputs found
Fully Integrated SAW-Less Discrete-Time Superheterodyne Receiver
No full textThere are nowadays strong business and technical demands to integrate radio- frequency (RF) receivers (RX) into a complete system-on-chip (SoC) realized in scaled digital processes technology. As a consequence, the RF circuitry has to function well in face of reduced power supply ( V DD ) while the CMOS device threshold voltage ( V th ) stays almost constant. Therefore, a conventional or continuous-time (CT) approach could not be efficiently utilized to design and implement the SoC, whereas a discrete-time (DT) approach offers the advantage for RF building blocks to operate properly in a smaller headroom. Furthermore, in finer CMOS technologies, transit frequency ( f T ) increases while CT RF building blocks do not benefit except for low-noise amplifiers (LNA). However, the performance of DT RF building blocks improves because of the higher sampling frequency ( f s ), lower power supply, and sharper clock edges provided by technology scaling. Nowadays, most integrated RF receivers are zero-IF (ZIF) because of well- known advantages such as less complicated architecture and easy channel-selection integration. They require many external duplexers, surface acoustic wave (SAW) filters, and switches, typically one per band, to attenuate out-of-band (OB) blockers. However, there are many issues associated with ZIF receivers such as time-variant DC offsets, sensitivity to 1 /f (flicker) noise, large in-band LO leakage, and second- order nonlinearity. For solving those issues, high-performance cellular SAW-less ZIF receivers now require extensive calibration efforts. For example, an intensive input 2 nd -order intercept point (IIP2) calibration must be simultaneously operated in the background with DC offset and harmonic rejection (HR) calibrations. Also, this calibration is susceptible to many factors such as variations in power supply, process corner, temperature, RF blocker frequency, local oscillator (LO) frequency, LO power, and channel frequency. On the other hand, a superheterodyne architecture pushes the IF frequency much higher so that the aforementioned problems are eliminated. Despite the advantages, the superheterodyne radios have not been utilized in cellular receivers simply because of the difficulty with integration of a high quality (Q)-factor band-pass filter (BPF) for image rejection in CMOS using CT circuitry. In this thesis, a new class of filters, i.e., charge-sharing (CS), is discussed that is being invented and developed to be utilized in not only superheterodyne but also in ZIF receivers. The proposed filter not only filters OB-blockers but also rejects interferers at the harmonic of LO frequency which is an extraordinary advantage especially for SAW-less receivers when there is no external filtering prior to the receiver input. Using these techniques, for the first-time ever, the superheterodyne receiver is proposed that meets the specification for SAW-less receivers. Chapter 1 briefly provides an overview of the blocks inside conventional RF radio transceivers. It mentions that there is a tendency in RF transceivers to support many of the multi-mode/multi-band communication standards such as Fourth Generation (4G) cellular application, Bluetooth, and Wi-Fi in one SoC. Also, the organization of the thesis has been described in details in this chapter. Chapter 2 establishes a common background for this thesis. Furthermore, it provides the background information for different sampling modes of operation such as subsampling (1x), half-rate sampling (2x) and full-rate sampling (4x) together with their frequency translations. Also, the technical mathematic background related to nonlinearity is briefly consolidated in this chapter. Chapter 3 discusses the first implemented DT superheterodyne receiver that utilizes the full-rate (4x) sampling mode of operation to solve a number of issues related to previous DT receivers. Chapter 4 explores performance capabilities and limitations of the proposed CS-BPF. A complex quadrature charge-sharing technique is proposed to implement a CS-BPF with a programmable bandwidth. It operates at the full sampling rate (4x), which was described in Chapter 2. Also, the complete noise analysis of the proposed CS-BPF is investigated. Additionally, the CT model of the CS-BPF is presented, and the filtering characteristic of proposed model has excellent agreement with the simulation result of the DT circuit. Finally, the implemented chip is fabricated in 65 nm CMOS, and the measured results are compared with simulations. Chapter 5 explores the possibility of creating a high quality (Q)-factor BPF at a very high IF because the CS-BPF proposed in Chapter 4 does not provide adequate selectivity. As a result, a highly reconfigurable superheterodyne RX is proposed that employs a 3rd-order complex IQ CS-BPF for image rejection and 1st-order feedback based RF-BPF for channel selection filtering. The proposed RX is the first attempt to achieve high-Q factor BPF at a very high-IF without replicas and images. Furthermore, the chip is fabricated in 65 nm CMOS technology, and the simulated results are completely verified by the measured results. Chapter 6 proposes and demonstrates the first-ever fully integrated SAW-less superheterodyne receiver for 4G cellular applications. The low-power DT RX introduces various innovations that simultaneously improve noise and linearity performance: a highly linear wideband noise-canceling LNTA, a blocker-resilient octal CS-BPF, and a cascaded harmonic rejection circuitry. The chip is fabricated in 28 nm CMOS technology, the characteristics of the fabricated chip are extensively measured, and the results are compared with the simulations. Chapter 7 draws the conclusions of this thesis work and provides recommendations for future research.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
All-Digital I/Q RF-DAC
No full textDue to the severe cost pressure of consumer electronics, a migration to an advanced nanoscale CMOS processes, which is primarily developed for fast and low-power digital circuits operating at low supply voltages, is necessary, but it forces wireless RF transceivers to exploit more and more digital circuitry. These basic CMOS properties tend to coerce the design of wireless functions towards the digital domain where transistors are utilized as switches rather than current sources. Within the past decade, there have been tremendous efforts towards implementing fully-digital or digitally-intensive RF transmitters in which they demonstrate transmitter designs that operate from baseband up to the pre-power amplifier (PA) stage entirely in the digital domain. In view of this digitalization, the RF transmitter modulator, being the nearest to the antenna as it converts digital baseband modulation samples into an RF waveform, is considered the most critical building block of the transmitter, and it can be in the form of either a polar, Cartesian (I/Q), or an outphasing topology. For wide modulation bandwidths, due to their direct linear summation of the in-phase (I) and quadrature-phase (Q) signals and thus the avoidance of the bandwidth expansion, Cartesian modulators are substantiated as the most appropriate choice over their polar or outphasing counterparts. Since the effective modulating sample resolution is the utmost important parameter as it directly impacts the achievable dynamic range, linearity, error vector magnitude (EVM), noise floor, and out-of-band spectral emission, this thesis proposes a wideband, high-resolution, all-digital orthogonal I/Q radio-frequency digital-to-analog (RF-DAC). Chapter 1 briefly provides an overview of the conventional RF radio building blocks. It is discussed that contemporary RF transceivers must support most of multi-mode/multiband communication standards such as Wi-Fi, Bluetooth, and Fourth Generation (4G) of 3GPP cellular. In Chapter 2, four types of RF transmitter architectures have been briefly described. The analog I/Q modulators are the most straightforward and widely employed RF transmitters. They are later replaced by analog polar counterparts to address their poor power efficiency and noise performance. On the other hand, in the analog polar RF transmitters, their related amplitude and phase signals must be aligned or spectral regrowth is inevitable. Utilizing digitally intensive polar RF transmitters mitigates the latter alignment issue. Nonetheless, polar transmitters suffer from an additional issue that is related to their nonlinear conversion of in-phase and quadrature-phase signals into the amplitude and phase representation. Therefore, the polar RF transmitters are not able to manage very large baseband bandwidth of the most stringent communication standards, therefore, reusing I/Q modulators based on digitally intensive implementation appears to be a reasonable approach to resolve this issue. The digital I/Q RF transmitters, however, suffer again from inadequate power efficiency. Moreover, the combination of in-phase and quadrature phase paths must be orthogonal to produce an undistorted-upconverted-modulated RF signal. In Chapter 3, a novel all-digital I/Q RF modulator is described. Employing an upconverting RF clock with a 25% duty cycle ensures the orthogonal summation of Ipath and Qpath, which avoids nonlinear signal distortion. It was clarified that electric summing of I and Q digital unit array switches is the most appropriate I/Q orthogonal summation approach. Moreover, to address all four quadrants of the constellation diagram, the differential quadrature upconverting RF clocks must be utilized. In addition, it was explained that employing switches instead of utilizing current sources leads to superior noise performance of the all-digital I/Q transmitter. In Chapter 4, a novel 2×3-bit all-digital I/Q (Cartesian) RF transmit modulator is implemented which operates as an RF-DAC. The modulator performs based on the concept of orthogonal summing, which is introduced and elaborated in Chapter 3. It is based on a time-division duplexing (TDD) manner of an orthogonal I/Q addition. By employing this method, a very simple and compact design featuring high-output power, power-efficiency and low-EVM has been realized. The resolution of the experimental RF-DAC presented in this work is only 3-bit (including one sign bit), but it will be demonstrated in the following chapters that the resolution can be increased to 8–12 bits in an unequivocal manner for utilization in multi-standard wireless applications. In Chapter 5, the system design considerations of the proposed high-resolution, wideband all-digital I/Q RF-DAC are discussed. It is demonstrated that the upsampling clock frequency (fCKR), DRAC resolution (Nb), and memory length (lmem) are three important parameters that affect the dynamic performance of the proposed RF-DAC. Based on system level simulation results and the limitation in implementing the RF-DAC test-chip, they are designated as fCKR=300 MHz, Nb=12 bit, and lmem=8 k-word. The effect of these parameters on the in-band as well as out-of-band performance of RF-DAC are investigated. It is concluded that exploiting 13 bits of resolution for quadrature baseband signals is sufficient to meet the most stringent communication requirements. In Chapter 6, the theory and the design procedure of an innovative, differential, orthogonal power combining network, which is employed in the proposed all-digital modulator, is thoroughly explained. It is demonstrated that, in order to maintain an orthogonal operation between the in-phase and quadrature-phase paths, the effect of the power combiner on the in-phase and quadrature-phase paths must be considered, otherwise, the linear summation will not occur. As a result, the EVM and linearity performance will diminish. The power combiner consists of a transformer balun as well as its related programmable primary and secondary shunt capacitors. In order to achieve high efficiency at full power of operation, a class-E type matching network is adopted and subsequently modified in order to obtain a minimum modulation error. A switchable cascode structure is exploited to mitigate a reliability issue as well as to perform a mixer operation. Moreover, utilizing a switchable cascode structure also improves the isolation between quadrature paths. Furthermore, it is explained that the power combiner efficiency is primarily related to the transformer balun efficiency. A procedure is introduced in order to design an efficient, compact balun transformer. Also, it is explained that the RF-DAC operates as a class-B power amplifier at the power back-off levels. As a result, its performance in the power back-off region is lowered. In Chapter 7, the implemented wideband, 2×13-bit I/Q RF-DAC-based all-digital modulator realized in 65-nm CMOS is presented. Employing the orthogonal I/Q combining approach which is proposed in Chapter 3 guarantees the isolation between in-phase and quadrature-phase paths. The 4×f0 off-chip single-ended clock is converted to a differential version employing an on-chip transformer. The wide swing, low phase noise, high-speed dividers are incorporated to translate the 4×f0 differential clock to the fundamental frequency of f0. In the meantime, the complementary quadrature sign bit is used to address four quadrants of the related constellation diagram. The 25% differential quadrature clocks are generated using logic-AND operation between 2×f0 differential clock and f0 differential quadrature clocks. The 12-bit DRAC is implemented employing a segmentation approach, which consists of 256 MSB and 16 LSB thermometer unit cells. The layout arrangement of the DRAC unit cell proves to be very crucial. It was concluded that the vertical layout would be the most appropriate selection. The LO leakage and I/Q image rejection technique as well as two DPD memoryless techniques of AM-AM/AM-PM and constellation mapping are introduced, which will be extensively utilized in the measurement segment. In Chapter 8, the high-resolution wideband 2×13-bit all-digital I/Q transmitter, which was introduced in Chapter 7, is thoroughly measured. First, the chip is tested in continuouswave mode operation. It is demonstrated that, with a 1.3V supply and, of course, an on-chip power combiner, the RF-DAC chip generates more than 21dBm RF output power within a frequency range of 1.36–2.51 GHz. The peak RF output power, overall system, and drain energy efficiencies of the modulator are 22.8 dBm, 34%, and 42%, respectively. The measured static noise floor is below -160 dBc/Hz. The digital I/Q RF modulator demonstrates an IQ image rejection and LO leakage of -65 dBc and -68 dBc, respectively. The RF-DAC could be linearized employing either of the two digital predistortion (DPD) approaches: memoryless polynomial or a lookup table. Its linearity is examined utilizing 4/16/64/256/1024-QAM baseband signals while their related modulation bandwidth can be as high as 154 MHz. Using AM-AM/AM-PM DPD improves the linearity by more than 25 dB while the measured EVM is better than -28 dB. Moreover, the constellation-mapping DPD is applied to the RF-DAC which improves linearity by more than 19 dB. These numbers indicate that this innovative concept is a viable option for the next generations of multi band/multi-standard transmitters. The realized demonstrator can perform as an energy-efficient RF-DAC in a stand-alone digital transmitter directly (e.g., for WLAN) or as a pre-driver for high-power basestation PAs. Chapter 9 draws the conclusions of the this thesis work and provides recommendations for future research and directions in the field of all-digital RF transmitters for wireless communication applications.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Millimeter-Wave Digitally-Assisted Frequency Synthesizer in CMOS
No full textMicroelectronicsElectrical Engineering, Mathematics and Computer Scienc
A Highly Selective, Very Linear Low Noise Transconductance Amplifier Capable of Large-Signal Handling for Current-Mode Receivers Front-End
No full textThe staggering advances in mobile phone industry and wireless technologies have led to abundance of wireless and cellular standards over the past few years. Most of the emerging radio standards (such as 4G LTE and WiMax) require flexible RF transceivers capable of handling various bandwidths and modulation scheme. Meanwhile, the demand by manufacturers for miniaturization, power and cost reduction have compelled further integration of RF transceivers by juxtaposing multiple RF SoC cores on a single silicon die. The prominent challenge in multi-radio chips is blocker interference. Blocker constraint in cellular radios is very stringent, requiring external SAW filters or high performance duplexers. However, SAW filters are bulky and expensive; plus, they reduce the receiver flexibility and degrade the RX sensitivity by a few dB. To circumvent these issues, “true SAW-less” receivers (by removing the SAW filter at the input of the RX) have been proposed in the literature. To achieve the ultimate flexible and multi-core radio operation, wide-band RX RF front-ends robust against interference, in excess of the requirements usually specified by a radio standard, are required. In this work, a highly selective, very linear LNTA capable of large-signal handling for current-mode RX front-ends is proposed and implemented in 65-nm CMOS technology. It is shown that by combining the on-chip high-Q bandpass filters with a push/pull class-AB common-gate stage, a large desensitization point (B1dB) and large-signal IIP3 of +8 dBm and +20 dBm, respectively, can be achieved, with 1.5 V supply voltages and 7.5 mA current consumption. Meanwhile, by applying noise cancellation technique, via an auxiliary push/pull class-AB common-source stage, a moderate NF of 5.9 dB is possible, which is a very competitive number for such value of B1dB.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
ADPLL Design for WiMAX
No full textThe frequency synthesizer, which functions as a local oscillator, is a critical block in the transceiver. It needs to meet very stringent specifications and consume as less power as possible. Design of a traditional charge-pump PLL as the frequency synthesizer in the advanced CMOS technologies in the transceiver of advanced communication systems proves to be not an easy work and is becoming difficult due to the supply shrink. The ADPLL system, which defines every essential block with digital interface, proves to be an excellent alternative. This thesis deals with the system level design of ADPLL for the WiMAX standard. The architecture of the ADPLL is presented, with the functional illustration for every building block, like DCO and TDC. The ADPLL system is modeled and described in Cadence using Verilog-AMS/Verilog. The performance of the system is analyzed in s-domain. Some advanced algorithms have been applied to the ADPLL system. The spur mechanism in the near-integer N cases is proposed and verified. The phase rotation algorithm and the FREF dithering algorithm have been adopted to effectively suppress these spurs. The top level issues of ADPLL are tackled, with emphasis on the test plan and the operation modes of the system. The behavior level simulation results of the system are presented and the performance summary is given. The transistor level design of a basic DPA is presented. The layout for the important blocks is done and the practical concerns of the DPA design are discussed. The post-extraction simulation results are shown.MicroelectronicsMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Design of RF Oscillators for Wireless Digital Transmitters
No full textCost reduction is one of the main driving forces for integration. As such, advanced CMOS technologies offer excellent digital functionality and high-density integration capabilities. Properties that persuade designers to exploit new digitally assisted approaches rather than following conventional analogue techniques. Using these new concepts, fully integrated transmitters that operate from baseband up to the pre-power amplifier (PA) stage entirely in the digital domain have become feasible. However, this imposes many coupling issues for different parts of the transceiver, such as the local oscillator. One of the primary building blocks of the transmitter is an oscillator and each modern digital transmitter has to have at least one oscillator, which normally has tough specifications imposed by the standard and transceiver architecture. This thesis focuses on the design of digitally controlled oscillators which could have excellent phase noise, very fine frequency resolution, small footprint and wide tuning range. Moreover, a simple yet an efficient architectural solution for the problem of local oscillator pulling, which will likely be the main cause degrading spectral purity of the TX output in multi radio SoCs has been proposed.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Low Power, All-Digital Fractional-N Frequency Synthesizers for Multi-GHz Applications
No full textDespite their high degree of reconfigurability and friendliness to technology scaling, traditional ADPLL-based frequency synthesizers tend to come at the price of increased power consumption at their feedback path, compared to charge-pump based solutions. The main power consumption bottleneck is the TDC that operates at the high output frequency rate. A modified version of the ADPLL architecture, that applies phase prediction and aligns the input and output clock edges by means of a digital-to-time converter (DTC), allows the operation of the phase detection entirely at the reference clock rate. To demonstrate the potential of the low-power phase prediction ADPLL architecture, two ADPLL test chips were designed, comprising a 2.5-5 GHz ring DCO and a wideband 10-16 GHz LC-DCO respectively. The two chips make use of the same DTC-TDC pair that consists identical delay generic cells for matched DTC and TDC gain values. The ADPLLs target multiple standards of wireline communication interfaces. At its typical configuration, the ring DCO ADPLL is expected to exhibit a power consumption of 3.9-5.3 mW resulting to a FoM of -164 dB, lower than any other reported ring-oscillator-based fractional-N PLL. The LC-DCO ADPLL power consumption varies from 10.2 to 13.8 mW and is the first fractional-N synthesizer among those targeting wireline communication for this range of frequencies. Additionally, this work introduces a cyclic DTC-TDC pair that can be rotated randomly in order to apply dynamic element matching of its elements and alleviate mismatch-induced spurs at low offsets of the spectrum in near-integer operation. The structure also allows dithering of the DTC control code in order to reduce quantization-induced spurs.ELCAMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
High-Purity Digitally Intensive Frequency Synthesis Exploiting Millimeter-Wave Harmonics
No full textThis thesis focuses on improving the phase noise and power efficiencyof millimeter-wave (mm-wave) frequency synthesizers in nanometer CMOS.The mm-wave frequency spectrum is widely adopted in various upcomingvolume commercial wireless applications. These new applications providemore interconnection between the physical and digital worlds. It entails ademand for high speed data communications and accurate object sensing,which are enabled by the large bandwidth available at mm-wave frequencies.These systems also require good signal-to-noise ratio (SNR) on mm-wavetransceivers. It sets stringent phase noise specifications on the mm-wavefrequency synthesizers. On the other hand, the power budget on the mm-wavefrequency synthesizers are limited for long battery lifetime and/or thermalreliability. The low phase noise should be achieved at high power efficiency.Advanced nanometer CMOS technologies are preferred for the integrationof mm-wave frequency synthesizers. The scaled transistor size favors the cointegration with baseband circuits and large-scale SoCs. The upgrowing speedof the MOSFETs also extends the upper limits on the operating frequencyof the CMOS circuits. On the other hand, the performance of mm-wavefrequency synthesizers suffers from various constraints and imperfections innanometer CMOS technologies. For example, the mm-wave oscillators isinferior in phase noise due to the low quality-factor LC tank and exacerbatedflicker noise upconversion. Mm-wave frequency dividers/multipliers are powerhungry and limit the power efficiency of the frequency synthesizers. There isa clear gap in performance between mm-wave and RF frequency synthesizers.Electronic
Power Efficient RF/mm-wave Oscillators and Power Amplifiers for Wireless Applications
No full textElectronic
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