112 research outputs found
Triazole-Tailored Guanosine Dinucleosides as Biomimetic Ion Channels to Modulate Transmembrane Potential
No full textA click ion channel platform has been established by employing a clickable guanosine azide or alkyne with covalent spacers. The resulting guanosine derivatives modulated the traffic of ions across the phospholipid bilayer, exhibiting a variation in conductance spanning three orders of magnitude (pS to nS). Forster resonance energy transfer studies of the dansyl fluorophore with the membrane binding fluorophore Nile red revealed that the dansyl fluorophore is deeply embedded in the phospholipid bilayer. Complementary cytosine can inhibit the conductance of the supramolecular guanosine channels in the phospholipid bilayers
Clock multiplication techniques for high-speed I/Os
No full textGeneration of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication techniques have been explored that can be suitable for high-speed wireline systems. With the emphasis on ring oscillator based architecture using cascaded stages, three possible architectures are explored.
First, a scrambling TDC (STDC) is presented to improve deterministic jitter (DJ) performance when used with a low-frequency reference clock. A cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage is used to achieve low random jitter in a power efficient manner. Fabricated in a 90nm CMOS process, the prototype frequency synthesizer consumes 4.76mW power from a 1.0V supply and generates 160MHz and 2.56 GHz output clocks from a 1.25MHz crystal reference frequency. The long-term absolute jitter of the 60MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter is 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz.
Second, a hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator-based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into an XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with an in-band phase noise floor of -104 dBc/Hz and 1.5 psrms integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8 dB.
Finally, an efficient clock generation, recovery, and distribution techniques for flexible-rate transceivers are presented. Using a fixed-frequency low-jitter clock provided by an integer-N PLL, fractional frequencies are generated/recovered locally using multi-phase fractional clock multipliers. Fabricated in a 65nm CMOS, the prototype transceiver can be programmed to operate at any rate from 3-to-10 Gb/s. At 10 Gb/s, integrated jitter of the Tx output and recovered clock is 360 fsrms and 758 fsrms, respectively.Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2019-05-01The student, Romesh Kumar Nandwana, accepted the attached license on 2017-04-17 at 15:09.The student, Romesh Kumar Nandwana, submitted this Dissertation for approval on 2017-04-17 at 15:42.This Dissertation was approved for publication on 2017-04-19 at 08:46.DSpace SAF Submission Ingestion Package generated from Vireo submission #10816 on 2017-08-10 at 15:05:48Made available in DSpace on 2017-08-10T20:32:59Z (GMT). No. of bitstreams: 3
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Previous issue date: 2017-04-19Embargo set by: Colleen Fallaw for item 102771
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Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemU of I Only Restriction Lifted for Item 102771 on 2019-08-11T09:15:10Z
Modelling Climate Change Impacts, Adaptation Strategies and Mitigation Potential in Horticultural Crops
No full textEnergy-efficient wireline transceivers
No full textPower-efficient wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are expected to be fully integrated. This thesis explores enabling techniques to implement such transceivers in both circuit and system levels. Specifically, three prototypes will be presented: (1) a 5Gb/s reference-less clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring oscillator-based fractional-N PLL as the low noise wide range DCO in the CDR loop; (3) a source-synchronous energy-proportional link with dynamic voltage and frequency scaling (DVFS) and rapid on/off (ROO) techniques to cut the link power wastage at system level. The receiver/transceiver architectures are highly digital and address the requirements of new receiver architecture development, wide operating range, and low power/area consumption while being fully integrated. Experimental results obtained from the prototypes attest the effectiveness of the proposed techniques.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-12-01The student, Guanghua Shu, accepted the attached license on 2016-09-28 at 11:50.The student, Guanghua Shu, submitted this Dissertation for approval on 2016-09-28 at 15:42.This Dissertation was approved for publication on 2016-09-30 at 13:20.DSpace SAF Submission Ingestion Package generated from Vireo submission #10172 on 2017-02-28 at 14:40:52Made available in DSpace on 2017-03-01T17:00:54Z (GMT). No. of bitstreams: 3
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Previous issue date: 2016-09-30Embargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:02:22Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:03:32Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:05:02Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 98665
Lift date: 2019-03-01T17:06:55Z
Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemLimited Restriction Lifted for Item 98665 on 2019-03-02T10:15:18Z
Women’s Entrepreneurship in Patriarchal Societies: The Case of Women’s Cooperatives in Turkey
No full textThis chapter explores the limits of and prospects for women’s entrepreneurship in patriarchal communities. The chapter investigates the patriarchal institutions and societal norms which work against women’s entrepreneurial activities and women’s presence in socioeconomic life in general. It also delves into women’s strategies to bargain, deal, and cope with patriarchal norms and institutions. The research is based on an extensive fieldwork on the case of Turkey, a country replete with patriarchal norms and institutions. The author conducts in-depth semi-structured interviews with members of women’s cooperatives throughout Turkey to better understand and explain the obstacles against women’s entrepreneurship in patriarchal societies and how women deal with these obstacles in their daily, entrepreneurial practices. In light of the fieldwork findings, the chapter concludes with policy implications and recommendations for more egalitarian and prosperous societies
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Responses of Soybean to Water Stress and Supplemental Irrigation in Upper Indo-Gangetic Plain: Field Experiment and Modeling Approach
No full textUnderstanding better the impacts of extreme dry spell regimes is essential for optimizing water management under a changing and variable climate. Using field experiments and modeling studies, we examined the impacts of dry spells in soybean and identified better management of water resources under varying water-scarce conditions. Field experimental data from soybean (PUSA-2614) experiments (July-Oct 2014; IARI, New Delhi, India) were used to calibrate and validate InfoCrop-Soybean model. This model was used to simulate optimal timing of irrigation under different dry spell scenarios. Results showed that plants subjected to water stress during flowering and vegetative growth stages had significantly lower yields and total dry matter (TDM). Supplemental irrigation significantly increased TDM and yields. InfoCrop-Soybean could simulate plant responses to water stress, at various stages of crop growth, and to supplemental irrigation, with acceptable accuracy. The crop model was further used to simulate impacts of dry spells at different intensities and durations on soybean growth and yields by creating drought scenarios for the New Delhi region using 36 years of weather data (1978–2014). Simulations showed that a 20% reduction in rainfall during any fortnight (every 15th day) of the cropping season does not affect crop yield significantly. However, dry spells (50% reduction in rainfall or more) in August and early September led to reduced yields, while supplemental irrigation during those dry spells could reduce yield losses. We envisage that the results of this study can help better manage water in soybean cultivation under dryland condition
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