1,721,038 research outputs found
A 152-mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG
No full textThis paper presents a low power multimedia system-on-chip (SoC) with full integration with fully programmable 3-D graphics, MPEG4 codec, H.264 decoder, and JPEG codec for mobile devices. The mobile unified shader in 3-D graphics engine provides fully programmable 3-D graphics with 35% area and 28% power reduction. Low-power lighting engine which employs logarithmic number datapath and the specialized lighting instruction enable 9.1 Mvertices/s vertex fill rate, which is 2.5 times improvement compared with previous works including transformations and OpenGL lighting. The SoC consumes less than 152 mW for video applications and less than 195 mW for 3-D graphics applications. The mobile unified shader and merged JPEG/MPEG4 codec reduce the silicon area and the SoC consumes 6.4 mm x 6.4 mm in 0.13 mu m complementary metal-oxide-semiconductor (CMOS) logic process
ENHANCED METAL-AFFINITY PARTITIONING OF GENETICALLY-ENGINEERED HIRUDIN VARIANTS IN POLYETHYLENE-GLYCOL DEXTRAN 2-PHASE SYSTEMS
No full textHirudin variants were constructed to exhibit an increased metal-binding affinity in an attempt to apply a metal-affinity partitioning process in a primary separation step for purification of hirudin. The hirudin variants were genetically engineered to contain additional surface-accessible histidines and produced by recombinant Saccharomyces cerevisiae. The partitioning behavior of these variants was compared with that of the wild type with a single surface-accessible histidine at position 51. Upon the addition of a small amount of Cu(II)IDA-PEG (Cu(II)iminodiacetic acid-polyethylene glycol) ligand to PEG/dextran two-phase systems, the hirudin variants with two or three surface-accessible histidines were more selectively partitioned into the PEG-rich phase than the wild type. Integrating protein engineering to metal-affinity partitioning offers the potential for general application of this technique to facilitate protein isolation, but the genetically engineered protein variants should be carefully constructed in a manner to minimize reduction of native protein activity
A Fixed-Point 3D Graphics Library with Energy-Efficient Cache Architecture for Mobile Multimedia Systems
No full textLow-power 3D graphics processors for mobile terminals
Full text linkA full 3D graphics pipeline is investigated, and optimizations of graphics architecture are assessed for satisfying the performance requirements and overcoming the limited system resources found in mobile terminals. Two mobile 3D graphics processor architectures, RAMP and DigiAcc, are proposed based on the analysis, and a prototype development platform (REMY) is implemented. REMY includes a software graphics library and simulation environment developed for more flexible realization of mobile 3D graphics. The experimental results demonstrate the feasibility of mobile 3D graphics with 3.6 Mpolygons/s at 155 mW power consumption for full 3D operation
A Low-Power Graphics LSI integrating 29Mb Embedded DRAM for Mobile Multimedia Applications
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A 210-mW graphics LSI implementing full 3-D pipeline with 264 Mtexels/s texturing for mobile multimedia applications
Full text linkA 121-mm(2), graphics LSI is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics and MPEG-4 applications. The LSI contains a RISC processor with a multiply-accumulate unit (MAC), a 3-D rendering engine, a programmable power optimizer, and 29-Mb embedded DRAM. The chip is built in a 0.16-mum pure DRAM technology to reduce the fabrication cost. Texture-mapped 3-D graphics with perspective-correct address calculation and bilinear MIPMAP filtering can be realized while consuming the low power with the help of depth-first clock gating, address alignment logic, and embedded DRAM. Programmable clocking allows the LSI to operate in lower, power modes for various applications. The chip consumes less than 210 mW, delivering 66 Mpixels/s and 264, Mtexel/s texture-mapped pixels with real-time special effects such as full-scene antialiasing and motion blur
Changes in alpha wave and state anxiety during ChunDoSunBup Qi-training in trainees with open eyes
No full textWe investigated the effects of ChunDoSurBup(CDSB) Qi-training, one of the Korean popular Qi-training systems, on EEG patterns, activation coefficients and state anxiety in 13 trainees with open eyes. CDSB Qi-training procedure consists of 3 stages: sound exercise, reciting Chunmoon, which is similar to a mantra; haeng-gong, a kind of body motion; and meditation. Compared to the control state (resting state before Qi-training), subjects reported less state anxiety, their activation coefficients decreased significantly during sound exercise and meditation in the occipital regions. Mean relative power and changes of mean absolute power of alpha wave increased significantly during sound exercise and meditation in the occipital regions. These results suggest that sound exercise and meditation in ChunDoSunBup Qi-training may reduce activation of the visual cortex and influence the thalamus and other functions of the brain. These could reduce anxiety levels and modulate the psychological, neurological, and physiological functions in man
A 155-mW 50-mvertices/s graphics processor with fixed-point programmable vertex shader for mobile applications
Full text linkA 36 mm(2) graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor, a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD) vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-mu m 6-metal standard CMOS logic process
A Low-Power and High-Performance 2D/3D Graphics Accelerator for Mobile Multimedia Applications
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