244 research outputs found
, 011604 (2016)]
No full textThe authors of a recently published letter1 state the purpose of their work as an evaluation of the stability of SiC/Si hetero-junctions at high temperatures. The central finding is that temperature annealing at 1100 °C leads to “catastrophic degradation” of “the diode behaviour of the initial p-Si/n-SiC junction.” The key electrical measurements that underpin these statements were performed on in-house SiC films,2 grown at 1000 °C on p-type Si substrates. The measurements were performed on bare Si samples and on n-SiC/p-Si samples before and after annealing. It was found that the 1100 °C annealing changes the initially measured n-type conduction, with a sheet resistance of RSiC=1354 Ω/□, to p-type conduction and a very small sheet resistance of 24 Ω/□. This change from 1354 Ω/□ (n type) before the annealing to only 24 Ω/□ (p type) after the annealing is the basis for the central statement of “catastrophic degradation,” which is specified as “shorting of the SiC film to the substrate upon annealing with consequent dominance of the carriers in the thick silicon substrate, with relatively high mobility.”Full Tex
Particle-Based Device Modeling
No full textThe key concepts in standard device modeling, such as continuous carrier concentration and continuous current, are questionable when the average number of carriers is smaller than one electron or one hole. This is not a rare scenario because the average number of minority carriers in semiconductor devices is almost always smaller than one carrier. In this paper, we demonstrate that the carrier generation, recombination, thermionic emission, and tunneling can be modeled by equations developed for single-carrier events.No Full Tex
Active Defects in 4H–SiC MOS Devices
No full textThe research findings presented in this thesis have provided several key contributions towards a better understanding of the SiC–SiO2 interface in SiC MOS structures. The electrically active defects directly responsible for degrading the channel-carrier mobility in 4H–SiC MOSFETs have been identified and a novel technique to detect these defects in 4H–SiC MOS capacitors has been proposed and experimentally demonstrated. With a better understanding of defects at the SiC–SiO2 interface two alternative gate oxide growth processes have been proposed to overcome the practical limitations associated with current NO-nitridation techniques in high-volume, production based oxidation furnaces. This work therefore contributes to the wider research effort towards improving the performance of SiC MOSFETs in several ways. The following paragraphs summarise the key conclusions that have been obtained as a result of this study.
Electrically Active Defects and the Channel-Carrier Mobility (Chapter 3)
A critical review of defects at the SiC–SiO2 interface exposed a few key discrepancies in both the current understanding of the dominant defects responsible for channel-carrier mobility degradation in 4H–SiC MOSFETs and in the current approach to characterise and evaluate the SiC–SiO2 interface. Firstly, it was recognised that the Shockley-Read-Hall statistical model, based on thermally activated transport for traps spatially located at the semiconductor-oxide interface, cannot be directly applied to describe the transfer mechanism between free conduction band electrons and the shallow NITs near EC. This implication tends to suggest that the NITs near EC in SiC MOS structures cannot be accurately examined using traditional MOS characterisation techniques that are based on this statistical model. Secondly, in accordance with the studies conducted by Saks et. al. [1-3], it was realized that channel-carrier mobility degradation in 4H–SiC MOSFETs is primarily due to the significantly reduced free electron density in the inversion channel. In light of this understanding, the interfacial defects that actively trap channel electrons under strong inversion conditions were considered to be dominant in these devices as opposed to the NITs near EC that are typically examined using conventional MOS characterisation techniques on N-type MOS capacitors in depletion. To further support this hypothesis, a theoretical analysis of the inversion carrier concentration using the charge sheet model was conducted to demonstrate that the NITs with energy levels corresponding to strong inversion are of key importance to the channel-carrier mobility.Thesis (PhD Doctorate)Doctor of Philosophy (PhD)Griffith School of EngineeringScience, Environment, Engineering and TechnologyFull Tex
On Memristive Threshold Logic Memory Networks
No full textThe ability of the human brain to provide different logic functions using physically similar cell structures is at the heart of its plasticity and ability to generalize. The principle of firing of neurons and connectivity of neuron networks gives rise to its generalized logical ability required to perform different cognitive tasks such as face recognition, object detection, identification and categorisation, rapidly, effortlessly and in real-time. These are computationally difficult tasks when performed in machine but the brain needs very low power and no pre-defined software.
Inspired by the principle of firing of neurons in the primate brain, and the ability of similar neuronal structures to perform different cognitive tasks, this thesis explores pro- grammable (mem)resistance-based threshold logic memory networks that are shown to perform basic logic functions to highly involved cognitive tasks such as face recognition and fast moving object detection, in a parallel, scalable hardware architecture.
To build neuromorphic systems in hardware, we use memristors, which are highly dense, non-volatile, and naturally amenable to be operated analogously to the biological synapse, to build a threshold logic cell. This cell is programmable and is the building block of memory networks that can be reconfigured to perform the cognitive tasks. The said memory networks also serve to shift focus from memory being a storage-only unit to being a computational unit as well, just as in the human brain.Thesis (PhD Doctorate)Doctor of Philosophy (PhD)School of Information and Communication TechnologyScience, Environment, Engineering and TechnologyFull Tex
Silicon Carbide as the Nonvolatile-Dynamic-Memory Material
No full textThis thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1]–[7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metal–oxide–semiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10]–[15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridation–oxidation–nitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitance–transient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiC–SiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiC–SiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10]–[16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metal–oxide– semiconductor field–effect–transistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.Thesis (PhD Doctorate)Doctor of Philosophy (PhD)School of Microelectronic EngineeringFaculty of Engineering and Information TechnologyFull Tex
Image Force Corrections to Tung's Inhomogeneous Schottky Barrier Model
No full textThe popular Tung model for Schottky barrier inhomogeneity considers how low-barrier patches (embedded in a high barrier background) impact the diode current. However, Tung's model fails to account for the image-force effect. We analyze how the image force alters the current through an inhomogeneous barrier and find that, in some circumstances, it will smooth the barrier, such that the current will effectively be that of a homogeneous diode. We also show that for a distribution of defect barriers and/or sizes, the diode current can be intermediate between that of a homogeneous diode and a diode dominated by the low-barrier patches. We calculate the parameter values associated with this transitional region. A survey of existing literature applications of Tung's model shows that many diodes are actually operating in this transition region, where Tung's equations are in error. We provide the corrected equations for this case and demonstrate their ability to model practical diode characteristics.No Full Tex
Pose-invariant Face Recognition through 3D Reconstructions
No full textPose invariance is a key ability for face recognition to achieve its advantages of being non-intrusive over other biometric techniques requiring cooperative subjects such as fingerprint recognition and iris recognition. Due to the complex 3D structures and various surface reflectivities of human faces, however, pose variations bring serious challenges to current face recognition systems. The image variations of human faces under 3D transformations are larger than that existing face recognition can tolerate. This research attempts to achieve pose-invariant face recognition through 3D reconstructions, which inversely estimates 3D shape and texture information of human faces from 2D face images. This extracted information is intrinsic features useful for face recognition which is invariable to pose changes. The proposed framework reconstructs personalised 3D face models from images of known people in a database (or gallery views) and generates virtual views in possible poses for face recognition algorithms to match the captured image (or probe view). In particular, three different scenarios of gallery views have been scrutinised: 1) when multiple face images from a fixed viewpoint under different illumination conditions are used as gallery views; 2) when a police mug shot consisting of a frontal view and a side view per person is available as gallery views; and 3) when a single frontal face image per person is used as gallery view. These three scenarios provide the system different amount of information and cover a wide range of situations which a face recognition system will encounter. Three novel 3D reconstruction approaches have then been proposed according to these three scenarios, which are 1) Heterogeneous Specular and Diffuse (HSD) face modelling, 2) Multilevel Quadratic Variation Minimisation (MQVM), and 3) Automatic Facial Texture Synthesis (AFTS), respectively. Experimental results show that these three proposed approaches can effectively improve the performance of face recognition across pose...Thesis (PhD Doctorate)Doctor of Philosophy (PhD)School of EngineeringScience, Environment, Engineering and TechnologyFull Tex
A Compact Model for SiC Schottky Barrier Diodes Based on the Fundamental Current Mechanisms
No full textWe develop a complete compact model to describe the forward current, reverse current, and capacitance of SiC Schottky barrier diodes. The model is based on the fundamental current mechanisms of thermionic emission and tunneling, and is usable over a large range of voltages, temperatures, and for a large range of device parameters. We also demonstrate good agreement with measured data. Furthermore, the development of this model outlines a methodology for transforming a tunneling equation into a compact form without numerical integration - this methodology can potentially be applied to other device structures.Full Tex
Regression Model for the Specific Contact Resistance of SiC Ohmic Contacts
No full textThe number of variables involved in the formation of Ohmic contacts to SiC is large, and their relationships to the final contact resistance are often unclear. As such, trial-and-error methods are typically employed to develop or improve SiC contacts. In pursuit of a better alternative, we developed and tested several regression models to predict the specific contact resistance of Ni, Ti, and Al based contacts on both n- and p-type SiC. Literature data was used to train linear regression, Gaussian process regression, and neural network (NN) ensemble models; of these, the NN ensemble was the most effective at predicting contact resistances. We then applied the model to optimize the annealing schedule for Ni contacts to n-type 4H-SiC, and Ti/Al contacts to p-type 4H-SiC. Finally, we use the model to generate optimal simultaneous contact recipes.No Full Tex
Design and Application of SiC Power MOSFET
No full textThis thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.Thesis (PhD Doctorate)Doctor of Philosophy (PhD)School of Microelectronic EngineeringFull Tex
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