21 research outputs found
TrainWare
No full textTraining convolutional neural network on device has become essential where it allows applications to consider user's individual environment. Meanwhile, the weight update operation from the training process is the primary factor of high energy consumption due to its substantial memory accesses. We propose a dedicated weight update architecture with two key features: (1) a specialized local buffer for the DRAM access deduction (2) a novel dataflow and its suitable processing element array structure for weight gradient computation to optimize the energy consumed by internal memories. Our scheme achieves 14.3%-30.2% total energy reduction by drastically eliminating the memory accesses
A Picosecond-Resolution Digitally-Controlled Timing Generator with One-Clock-Latency at Arbitrary Instantaneous Input
No full text1
PowerField
No full textTransient temperature-to-power conversion is as important as steady-state analysis since power distributions tend to change dynamically. In this work, we propose PowerField framework to find the most probable power distribution from consecutive thermal images. Since the transient analysis is vulnerable to spatio-temporal thermal noise, we adopted a maximum-a-posteriori Markov random field framework to enhance the noise immunity. The most probable power map is obtained by minimizing the energy function which is calculated using an approximated transient thermal equation. Experimental results with a thermal simulator shows that PowerField outperforms the previous method in transient analysis reducing the error by half on average. We also applied our method to a real silicon achieving 90.7% accuracy
A pattern-dependent injection-locked CDR for clock-embedded signaling
No full textThis paper presents a CDR architecture for clock-embedded signaling. To suppress the effect of data-dependent jitter of the conventional DLL-based approach, we propose a pattern-dependent injection-locking scheme in a PLL-based clock recovery circuit. It achieves both benefits of PLL and DLL, the input jitter filtering and the clearance of accumulated VCO jitter, respectively. A jitter analysis is also presented to develop a design strategy for the optimal extraction of injection timing from random data stream. The CDR, implemented in a 28 nm CMOS, achieves a data rate of 12.5 Gb/s with a 13.7 dB-loss channel and verifies the validity of the analysis.11Nsciescopu
A 250μW 2.4GHz Fast-Lock Fractional-N Frequency Generation for Ultra-Low-Power Applications
No full textThis brief presents a fast-lock 2.4-GHz fractional-N phase-locked loop (PLL) for ultralow-power applications. To minimize the power consumed by all the other circuits except for the main oscillator, we propose a master-slave PLL structure in which a low-frequency master PLL is followed by a slave injection-locked oscillator operating at high frequency. A frequency-error compensation circuit is also implemented in the slave oscillator to eliminate possible drift in the free-running frequency. With a fractional-N coarse-lock unit in the master PLL and a fine frequency initialization unit in the slave oscillator, the PLL supports two fast-lock modes: 1) start-up locking from deep-power-down mode and 2) instantaneous relocking from standby mode. The implemented PLL in 65-nm complementary metal-oxide-semiconductor (CMOS) consumes 250 μW from a 0.8-V supply, demonstrating a power efficiency of 0.102 mW/GHz. The PLL performs the two fast-lock operations with lock times of less than 22 μs from deep power down and 1 μs from standby, respectively.112sciescopu
에너지 효율적인 심층 컨볼루셔널 신경망 프로세서 및 DRAM 내부 연산 프레임워크
No full text학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2019.2,[vii, 84 p. :]Recent deep convolutional neural networks (CNNs) are outperforming conventional hand-crafted algorithms in a wide variety of intelligent vision tasks, but they require billons of operations and hundreds million of weights. To process large-scale CNNs energy-efficiently, three generations of CNN hardware are designed in this dissertation. The first two generations are CNN processors based on the conventional Von Neumann architecture, and the third generation CNN hardware is based on in-DRAM processing framework that does not obey Von Neumann architecture. The first generation primitive CNN processor integrates dual-range multiply-accumulate (MAC) blocks by exploiting the statistics of input feature values to reduce energy consumption of MAC operations. Also, tile-based computing method is proposed in the primitive CNN processor. In result, it achieves 1.42TOPS/W energy efficiency in the LeNet-5 CNN model. The second generation advanced CNN processor operates at near-threshold voltage (NTV) to reduce energy consumption furthermore. It also features a newly proposed enhanced output stationary dataflow (EOS) and two-stage big and small on-chip memory architecture, resulting in up to 1.15TOPS/W energy efficiency in the VGG-16 model. Finally, the third generation in-DRAM processing binary CNN hardware processes dominant convolution operations by serially cascading in-DRAM bulk bitwise operations. To this end, we first identify the problem that the bitcount operations with only bulk bitwise AND/OR/NOT incur significant overhead in terms of delay when the size of kernels gets larger. Then, we not only optimize the performance by efficiently allocating inputs and kernels to DRAM banks for both convolutional and fully-connected layers through design space explorations, but also mitigate the overhead of bitcount operations by splitting kernels into multiple parts. Partial sum accumulations and tasks of the other layers such as max-pooling and normalization layers are processed in the peripheral area of DRAM with negligible overheads. In results, our in-DRAM binary CNN processing framework achieves 19x-36x performance and 9x-14x EDP improvements for convolutional layers, and 9x-17x performance and 1.4x-4.5x EDP improvements for fully-connected layers over previous PIM technique in four large-scale CNN models. Also, it shows 3.796TOPS/W energy efficiency in AlexNet CNN model.한국과학기술원 :전기및전자공학부
SIMD 구조의 피연산자 값 지역성을 활용한 타이밍 오류 제거 기법
No full text학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 2014.2
,[vi, 58 p. :]A significant energy is consumed by the voltage guardband to ensure correct operations in modern processors even under the rarely occurring worst-case conditions. Furthermore, worsening PVT variation is making the voltage guardband grow. This bounded voltage scaling trend conflicts with the strong need for low-power, low-energy solutions arise from ever tightening power budget and dark silicon issue. Consequently, better-than-worst-case design is becoming a promising solution as it achieves a significant amount of energy savings by removing the voltage guardband and scaling the supply voltage additionally.
In order to guarantee correct operations of a processor in the better-than-worst-case-design, Razor flip-flops and Instruction Replay are widely used to detect and correct timing errors induced by voltage over-scaling. However, the potential gain from scaling the supply voltage is limited as error rate and the following occurrence of Instruction Replay increase. Moreover, throughput and energy loss caused by replaying the pipeline is a critical problem in SIMD architecture.
In this work, an error masking scheme targeted for integer additions in SIMD architecture is proposed. The masking is done by applying the concept of partial reuse to potential erroneous instructions. Two critical observations are conducted in order for the reuse and mask scheme to work properly: temporal operand value locality and operand value locality across SIMD lanes. Simulation results based on the real operands sampled from 15 CUDA benchmarks strongly prove that both temporal operand value locality and operand value locality across lanes exist in SIMD architecture.
In addition, detailed implementations for reuse and mask are proposed in this work. Masking logic is inserted to integer ALUs of each SIMD lanes. A single reuse table is implemented for an entire SIMD processor, and it is accessible before and after the execution stage.
Intensive simulations on 15 CUDA benchmarks were performed to evaluate our proposed implementation. 10 design variants of our scheme are analyzed to get an optimal solution. Our result show that a significant amount timing errors are masked by the proposed design. Also, throughput comparable to that of error-free execution is achieved, which is a crucial benefit for throughput-oriented SIMD architecture. Finally, our scheme obtains up to 5.1% improvement in energy consumption and 30% improvement in EDP when compared to energy optimal point of Razor only design.한국과학기술원 :전기및전자공학과
eSRCNN: A Framework for Optimizing Super-Resolution Tasks on Diverse Embedded CNN Accelerators
No full textCNN-based Super-Resolution (SR), the most representative of low-level vision task, is a promising solution to improve users’ QoS on IoT devices that suffer from limited network bandwidth and storage capacity by effectively enhancing image/video resolution. Although prior accelerators to embed CNN show tremendous performance and energy efficiency, they are not suitable for SR tasks regarding off-chip memory accesses. In this work, we present eSRCNN, a framework that enables performing energy-efficient SR tasks on diverse embedded CNN accelerators by decreasing off-chip memory accesses. To reduce off-chip memory accesses, our framework consists of three steps: a network reformation using a cross-layer weight scaling, a precision minimization with priority-based quantization, and an activation map compression exploiting a data locality. As a result, the energy consumption of off-chip memory accesses is reduced up to 71.89% with less than 3.52% area overhead
A PVT-robust Customized 4T Embedded DRAM Cell Array for Accelerating Binary Neural Networks
No full textDeep neural networks (DNNs) are widely used for real-world applications. However, large amount of kernel and intermediate data incur a memory wall problem in resource-limited edge devices. The recent advances of a binary deep neural network (BNN) and a computing inmemory (CIM) have effectively alleviated this bottleneck especially when they are combined together. However, previous CIM-based accelerators for BNN are highly vulnerable to process/supply voltage/temperature (PVT) variation, resulting in severe accuracy degradation which makes them impractical to be employed in real-world edge devices. To address this vulnerability, we propose a PVT-robust accelerator architecture for BNN with a computable 4T embedded DRAM (eDRAM) cell array. First, we implement the XNOR operation of BNN in a time-multiplexed manner by utilizing the fundamental read operation of the conventional eDRAM cell. Next, a PVT-robust bit-count based on charge sharing is proposed with a computable 4T eDRAM cell array. In result, the proposed architecture achieves 6.9× less variation in PVT-variant environments which guarantees a stable accuracy and 2.03-49.4× improvement of energy efficiency over previous CIM-based accelerators
