1,721,049 research outputs found
DC-balanced block inversion coding for high-speed links
No full textA new 4B5B block inversion coding is proposed for dc-balanced transmission in high-speed optical parallel links. An 8-bit byte is partitioned into two 4-bit data and converted to two 5-bit blocks by an inversion encoding. The proposed coding greatly reduces circuit complexity with the minimum latency overhead of one clock for the encoder and none for the decoder. The maximum run length is 11.open11sciescopu
Segmented group-inversion coding for parallel links
No full textA new segmented group-inversion coding is proposed to achieve current balancing in single-ended parallel data transmission. With minimal increase in number of pins, the proposed coding reduces the difference between the number of ZEROS and ONEs to only 0 or 2. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with greatly simplified logic circuits. Generalization for the optimum grouping is also presented. A transmitter with 16-bit link was designed for verification. The proposed coding scheme is suitable for gigabit parallel links to reduce the simultaneous switching noise.X116sciescopu
A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling
No full textThis paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit that utilizes common-mode clock-embedded signaling (CM-CES) and injection locking techniques to reduce design complexity for the half-rate data recovery. In the proposed receiver, the use of wideband injection-locked oscillator (ILO) greatly suppresses its phase noise while the narrowband digital phase tracking loop (DPTL) tunes retiming phase. For wide-range and continuous-rate operation, four circuit techniques have been adopted: a VCO with active inductance load for low VCO gain at high frequency, a wide-range digitally-controlled delay line (DCDL) with adaptive band selection, a linearized delay control unit with CM-to-delay conversion technique, and a coarse frequency detection scheme to drive the free-running oscillator frequency toward injection locking. The prototype CDR, fabricated in low power CMOS 65 nm technology, successfully detects 0.8-6.5 Gb/s data rates over 5 '' FR4 trace with 2(31) - 1 PRBS pattern satisfying BER < 10-12. The power efficiency was 2.4 mW/Gb/s at 6.5 Gb/s.110sciescopu
Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS
No full textThis paper describes the characteristics of a halfrate clock-embedded source-synchronous signaling scheme to identify its constraints and to optimize the transceiver topology in the presence of a band-limited channel. The proposed signaling combines the half-rate clock to the common mode of the differential data with its mixing phase off by 0.5 UI. Two transceivers with resistive-load and inductive-load receivers are implemented in 130-nm CMOS technology to verify their feasibility for use as serial links. The prototype transceivers achieve a wide operating frequency range 2.25-6 and 5.6-8 Gb/s, respectively, satisfying bit error rate of < 10(-12) measured at Tx-Rx linked configuration by 5-in-long FR4 trace with 2(31) -1 PRBS. The power efficiencies of transceivers at maximum data rates are 6.4 and 4.6 mW/Gb/s, respectively.X1134sciescopu
A PEAK-CURRENT-REDUCED FULL-SWING CMOS OUTPUT DRIVER
No full textThis letter proposes an output driver which reduces simultaneous switching noise without degradation of rise/fall time. At the start of transition period. the driver optimally uses both VDD and VS S current by switching of on-chip bypass capacitors. The proposed driver achieves 27-percent reduction in peak current with faster transition time.open11sciescopu
Multilevel differential encoding with precentering for high-speed parallel link transceiver
No full textA multilevel differential encoding scheme is proposed as a new approach for use in high-speed parallel transceiver systems. While incurring little or no increase in the number of links, the proposed encoding scheme overcomes two major problems in single-ended parallel links-reference ambiguity and power-line fluctuations. The proposed scheme transmits differentially encoded data among the pins and adjusts the driving current to be constant so as to minimize the L(di/dt) switching noise on the output driver power lines. A new precentering scheme is also applied to maximize the horizontal eye opening by centering all signals during a predefined time before the start of the next symbol transition. To verify the proposed schemes, a transceiver chip was designed and fabricated in 0.25-mu m CMOS technology. The chip, which consists of 1 parallel links with only three ground and three supply pins for the output drivers, employs a three-level differential encoding scheme to achieve a maximum data rate of 1.8 Gb/s with a bit error rate of less than 10(-12).X117sciescopu
A Low-Power Class-AB Gm-Based Amplifier With Application to an 11-bit Pipelined ADC
No full textA Gm-based amplifier is proposed for the use in low-voltage and low-power switched-capacitor circuits. At the input stage of the amplifier, a common-mode current-suppression scheme effectively suppresses the common-mode current with the differential-mode current even amplified, resulting in decrease in dc power consumption. At the output stage of the amplifier, a self-biased cascode configuration adaptively changes bias voltages to achieve both the cascode operation for high gain and digital switching operation for fast transients. The proposed amplifier is applied to a design of an 11-bit pipelined ADC with a 0.13-mu m CMOS process. The implemented analog-to-digital converter consumes 80 mu W from a single 0.7 V supply at 2.5 MS/s. It achieves an effective number of bit of 9.72 bit without any calibration scheme and a figure of merit of 37.8 fJ/c-s at near Nyquist rate.1133sciescopu
CHARGE-TRANSFERRED PRESENSING, NEGATIVELY PRECHARGED WORD-LINE, AND TEMPERATURE-INSENSITIVE POWER-UP SCHEMES FOR LOW-VOLTAGE DRAMS
No full textA 256-Mb SDRAM is implemented with a 0.12-mum technology to verify three circuit schemes suitable for low-voltage operation. First, a new charge-transferred presensing achieves fast stable low-voltage sensing performance without additional bias levels required in conventional charge-transferred presensing schemes. Second, a negative word-line scheme is proposed to bypass the majority of discharging current to VSS. Without switching signals, main discharging paths are automatically switched from VSS to VBB2 in response to the voltage of each discharging node itself. Finally, to initialize internal nodes during power-up, a temperature-insensitive power-up pulse generator is also proposed. The temperature coefficient of the setup voltage is adjustable through optimization of circuit parameters.X115sciescopu
A Slew-Rate Controlled Transmitter to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines
No full textA single-ended transmitter eliminates the crosstalk-induced jitter at receiver by controlling the slew rates of the signal at transmitter for the even and odd modes of two parallel coupled microstrip lines. The transmitter chip in a 0.18 mu m CMOS process reduces the total RX jitter by about 38 ps (53%) for the data rates from 2.6 to 5 Gbps, and increases the horizontal eye-opening (BER < 1E-12) by about 21% at 5 Gbps.110sciescopu
An OTA with Positive Feedback Bias Control for Power Adaptation Proportional to Analog Workloads
No full textThis paper reports an adaptive positive feedback bias control technique for operational transconductance amplifiers to adjust the bias current based on the output current monitored by a current replica circuit. This technique enables operational transconductance amplifiers to quickly adapt their power consumption to various analog workloads when they are configured with negative feedback. To prove the concept, a test voltage follower is fabricated in 0.5-mu m CMOS technology. Measurement result shows that the power consumption of the test voltage follower is approximately linearly proportional to the load capacitance, the signal frequency, and the signal amplitude for sinusoidal inputs as well as square pulses.110sciescopuskc
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