41 research outputs found
Flow Model Can Give You Optimal and Diverse Design Guidance for TSV Array Placement in HBM
No full textElectrical Performance Comparison between Coaxial and Non-coaxial Silicone Rubber Socket
No full textThis paper compared a coaxial silicone rubber socket and non-coaxial socket for high-performance package test. The silicone rubber socket is a kind of the elastomer test sockets consisting of metal powders in the elastomer material. The noncoaxial silicone rubber socket may have the limited electrical performances due to its pitch. Because the pitch is determined by the package's footprint. For this, the coaxial silicone rubber socket was proposed to provide the improved insertion loss and crosstalk noise. The coaxial silicone rubber socket has extra ground powders around the signal powders to configure the coaxial structure. This coaxial structure has advantages in characteristic impedance matching and crosstalk noise reduction. Therefore, this paper compared the insertion loss and crosstalk for the non-coaxial and coaxial silicone rubber socket
Deep Reinforcement Learning-based Through Silicon Via (TSV) Array Design Optimization Method considering Crosstalk
No full textIn this paper, we propose the through silicon via (TSV) array design optimization method using deep reinforcement learning (DRL) framework. The agent trained through the proposed method can provide an optimal TSV array that minimizes far-end crosstalk (FEXT) in one single step. We define the state, action, and reward that are elements of the Markov Decision Process (MDP) for optimizing the TSV array considering FEXT and train a deep q network (DQN) agent. For verification, we applied the proposed method to a 3 by 3 through silicon via array at stacked DRAM of High Bandwidth Memory (HBM). The network converged well, and as the result, the proposed method provided the optimal design that satisfies the target FEXT in which 3 dB lower than the initial design
딥 뉴럴 네트워크 추론을 위한 아날로그 기반의 뉴로모픽 시스템에서의 신호 무결성을 고려한 대규모 고속 멤리스터 크로스바 어레이 설계
No full text학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2020.2,[iii, 40 p. :]In this paper, we first propose a large-scale high-speed memristor crossbar array considering signal integrity for deep neural network inference. This paper aims to design the interconnection of memristor crossbar array for the highest accuracy of inference. For this, we modeled and implemented the entire computational process for inference in addition to structural design and analysis. To get accurate inference results over a wide operating frequency band, we designed interconnections and an array that can cancel the ringing. Also, the signal integrity analysis in the designed structure was used to understand the phenomenon and to check the eye diagram. In order to verify the proposed design, DNN is implemented through hybrid-circuits model and inference accuracy was confirmed. Finally, it is confirmed that the accuracy is significantly improved compared to the existing array having the same network size.한국과학기술원 :전기및전자공학부
Finding the Missing Link between Corporate Social Responsibility and Firm Competitiveness through Social Capital: A Business Ecosystem Perspective
No full textThere are existing studies that successfully show the impact of corporate social responsibility (CSR) on firms’ financial performance. However, limited attention is paid to its impact on the business ecosystem. CSR could be seen as an investment for building a sustainable business ecosystem, which enhances the competitiveness of this system’s members. In that context, this study apprehends and captures the virtuous cycle of firm competitiveness. On analyzing data from interviews with seven firms, the study offers four propositions identifying the structure of the virtuous cycle linking CSR activities to firm competitiveness through the accumulation of social capital within business ecosystems. Based on those propositions, the study offers new insights into CSR research for academics and strategic planning guidelines for managers that integrate social and economic values for a sustainable business ecosystem and firm competitiveness
Learning Super-scale Microbump Pin Assignment Optimization for Real-world PCB Design with Graph Representation
No full texthe requirement for higher bandwidth in computing systems has increased. Hence, the number of I/Os of 2.5D/3D ICs is also increasing for dense interconnections. Accordingly, the pin count of the microbump package is getting larger along with its signal integrity issues. In this paper, we propose a deep reinforcement learning (DRL)-based pin assignment optimization method that represents microbumps on graphs to minimize signal integrity degradation. The pin assignment task of microbumps is formulated by modifying the maximum independent set (MIS) problem which is a graph combinatorial optimization task. The proposed method is designed by making adjustments to a state-of-the-art DRL-based MIS solver. The graph-based learning method brings advantages in that it can assign pins to pin maps of any shape on a very large scale. We verify that the proposed DRL-based method is effective by comparing it with a meta-heuristic method, a conventional method for solving optimization tasks, called genetic algorithm
Crosstalk-included PAM-4 Worst Eye Diagram Estimation Method for High-speed Serial Links
No full textIn this paper, we first propose a crosstalk-included pulse amplitude modulation-4 (PAM-4) worst eye diagram estimation method. The proposed method is based on the conventional peak distortion analysis (PDA) method. Compared to the non-return-to-zero (NRZ), the PAM-4 has 3 single bit responses (SBRs) due to the 4-level amplitude modulation. To consider worst crosstalk effects, the main idea is to take 3-level transition crosstalk responses as input when estimating each level-transition worst eyes by the PDA. By superposition of the estimated 1-level, 2-level and 3-level worst eyes, a PAM-4 worst eye contour can be provided as an innermost contour. For verification, we compared the estimated PAM-4 worst eye diagrams with those at bit-error-ratio (BER) 10-12 by the statistical eye simulator using input output buffer information specification-algorithmic modeling interface (IBIS-AMI). We compared the results in various cases: with 1 near-end crosstalk (NEXT) aggressor (aggr); with 1 NEXT and 1 far-end crosstalk (FEXT) aggrs; with 2 NEXT and 1 FEXT aggrs. The error rates of eye widths and heights between the proposed method and the simulator were 6.3 % and 4 % respectively. Moreover, we compared the computing time. The computing time of the proposed method was within 50 ms in all the cases, however that of the simulator increases from 10.5 s to 21.7 s as the number of aggrs increases
