1,721,038 research outputs found
Dataset for: A computationally efficient Verilog-A ReRAM model
No full textData set for paper of same name. This is a Verilog-A ReRAM model that corresponds to the behavior of a physical TiO2-based sample manufactured in Nano Group, ECS, University of Southampton. The model is ready for use and can be compiled in any electronics circuit simulator that supports Verilog-A models.</span
Seamlessly Fused Digital-Analogue Reconfigurable Computing using Memristors
No full textDataset supports:
Serb, A. at al (2018). Seamlessly Fused Digital-Analogue Reconfigurable Computing using Memristors. Nature Communications.
Each zip file contains the data for an individual figure (FX, where X is the figure number) or supplementary figure (SFX). Within each zip file there is a bespoke documentation for each panel of the figure, which also covers the contents of each individual file within the zip directory.</span
Dataset for the article: "Measured Behaviour of a Memristor-Based Tuneable Instrumentation Amplifier"
No full textThe excel file includes the measured data used for generating the Fig 2 to 5 in the paper 'Measured Behaviour of a Memristor-Based Tuneable Instrumentation Amplifier'.
The PNG file inclues the Fig 2 to 5 in the paper which were generated based on the data in the excel file. The figures are as follows:
Fig2. Impedance-frequency function of TiOx/Al2O3 10×10µm2 memristor devices.
Fig3. Gain response of the instrumentation amplifier for a set of memristor resistances and a based line given by 30kΩ discrete resistor.
Fig4. THD+N of the instrumentation amplifier with input signal amplitude from 30mV to 300mV.
Fig5. THD+N of the instrumentation amplifier uses 3 memristors compare with uses 1 memristor.</span
Seamlessly fused digital-analogue reconfigurable computing using memristors
No full textAs the world enters the age of ubiquitous computing, the need for reconfigurable hardware operating close to the fundamental limits of energy consumption becomes increasingly pressing. Simultaneously, scaling-driven performance improvements within the framework of traditional analogue and digital design become progressively more restricted by fundamental physical constraints. Emerging nanoelectronics technologies bring forth new prospects yet a significant rethink of electronics design is required for realising their full potential. Here, we lay the foundations of a design approach that fuses analogue and digital thinking by combining digital electronics with analogue memristive devices for achieving charge-based computation; information processing where every dissipated charge counts. This is realised by introducing memristive devices into standard logic gates, thus rendering them reconfigurable and capable of performing analogue computation at a power cost close to digital. The versatility and benefits of our approach are experimentally showcased through a hardware data clusterer and an analogue NAND gate.<br/
Dataset for A computationally efficient Verilog-A ReRAM model (v.2)
No full textThis is an updated version of the data set for paper of same name. (The previous version has a DOI of 10.5258/SOTON/D0082). This is a Verilog-A ReRAM model that corresponds to the behavior of a physical TiO2-based sample manufactured in Nano Group, ECS, University of Southampton. The model is ready for use and can be compiled in any electronics circuit simulator that supports Verilog-A models.
A minor version change to v.2.1 occured on 3/1/2018 (see Change Log).</span
An RRAM biasing parameter optimizer
Full text linkResearch on memory devices is a highly active field, and many new technologies are being constantly developed. However, characterizing them and understanding how to bias for optimal performance are becoming an increasingly tight bottleneck. Here, we propose a novel technique for extracting biasing parameters, conducive to desirable switching behavior in a highly automated manner, thereby shortening the process development cycles. The principle of operation is based on: 1) applying variable amplitude, pulse-mode stimulation on a test device in order to induce switching multiple times; 2) collecting the data on how pulsing parameters affect the device’s resistive state; and 3) choosing the most suitable biasing parameters for the application at hand. The utility of the proposed technique is validated on TiOx-based prototypes, where we demonstrate the successful extraction of biasing parameters that allow the operation of our devices both as multistate and binary resistive switches
Measured behaviour of a memristor-based tuneable instrumentation amplifier
No full textA memristor-based tuneable instrumentation amplifier whose gain value can be adjusted by memristor is implemented and measured. While memristive devices are suitable for implementing reconfigurable circuit designs, their non-linear characteristic and parasitic capacitance can impact performance. In this work, an instrumentation amplifier is built on breadboard using off-the-shelf OpAmps and packaged memristor devices and its performance is assessed. Results are compared with an identical design that preplaces memristors with resistors (losing reconfigurability in the process), to reveal the effects arising from the memristor's characteristics. Effects on frequency response, common mode rejection ratio (CMRR) and total harmonic distortion plus noise (THD+N) are observed. The memristor-based instrumentation amplifier begins to be affected by the non-linearity of the device only when the base OpAmps have a THD value below 0.3%. The bandwidth of the instrumentation amplifier is limited by the parasitic capacitance of memristors, and CMRR has small variation when using memristor to replace the original gain resistor. The THD+N value is large compared with identical design, but it is also found that by applying multiple memristors the increasing of THD+N can be relieved.</p
Bidirectional volatile signatures of metal-oxide memristors-Part II: modeling
No full textVolatility in metal-oxide resistive random access memory (RRAM) families has mostly been treated as an unwanted side-effect, although recently there are trends to interpret such behavior as an additional technological feature. To date, the field has seen early demonstrations of possible applications that harness volatility. Moreover, some work has been conducted to understand both the mechanisms responsible for this behavior. In the context of modeling RRAM volatility, we still lack a comprehensive model that could allow simulations in a larger scale. In an attempt to fill this gap, this work presents a modeling framework that can account for RRAM relaxation characteristics. Specifically, we show how volatility can be simulated to significant accuracy when the resistive state (RS) of a device as well as the stimulus protocol in use are well-defined. Importantly, our approach is solely data-driven and decoupled from previous physical modeling studies on volatility. Our results work for both stimulation polarities and are consistent for a number of TiOx devices in use. Moreover, the mathematical relations that unfold via modeling volatility provide further intuition on the effect that invasive protocols can have on this technology. This modeling solution enables more advanced studying of memristive technologies in one hand, as well as more intricate designs of larger systems that can account for transient RRAM changes over time
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