1,720,983 research outputs found
The right tool for the right job: developing tools to overcome the RRAM testing bottleneck
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Dataset in support of the Southampton doctoral thesis 'Ultra-Fine Signal Classification Using Memristor-Enabled Hardware'
No full textThe data is in the form of .csv file, created from Cadence Virtuoso. They correspond to three circuits simulation results in the doctoral thesis 'Ultra-Fine Signal Classification Using Memristor-Enabled Hardware'.</span
Ultra-fine signal classification using memristor-enabled hardware
No full textNeural activity recording system promotes the development of diagnostic and therapeutic programs and neuroscience research. Direct recordings of neural signals from the brain have helped scientists access to study and unlock the secrets of neural coding gradually. This can be realised by applying implantable neural recording systems to monitor and record neural signals. Then, the neural information can be transmitted to the external device for processing, storage or application. However, the power consumption of the neural recording system is the primary constraint to monitoring large groups of neurons. It leads the development of neural recording systems in two directions: 'high-channel-count but wired' and 'wireless but low-channel-count'. To address the power issue, we proposed a neural front-end that aims to detect neural spikes by thresholding and output as one-bit digital data so that the afterwards processing can only work on spikes rather than processing all the data points. The most significant feature is that we induce memristors as trimming devices to tune the threshold voltage for spike detection.Meanwhile, it contributes to rejecting up to 50mV DC offset from electrodes. The measurement presents that the memristor-based pre-amplifier is capable of achieving above 95% spike detection accuracy with hundreds of nanowatt power consumption per channel. This design indicates a promising approach to conduct spike-detection on-chip with low power consumption and demonstrates the potential of a hybrid memristor/CMOS circuit for power-efficient large-scale neural interfacing application
High-sensitivity memristor-based threshold detection
No full textThe ability to read brain activity across large swathes of cortex at very high resolution both spatially and temporally is a holy grail objective of modern neuroscience. In this endeavour, the minuteness of neural signals arriving from needle probes (10s to 100s of μV) poses a significant challenge, typically solved using high spec amplifiers. However, when the objective is to detect neural spikes the input signals of interest are inherently sparse, and much energy is spent amplifying data points that will be ultimately discarded. In this work we propose that a possible solution is to distance ourselves from the need to amplify the neural waveforms, and instead opt for performing threshold detection directly on the input signal; which is often sufficient to detect neural spiking. We thus present a high sensitivity threshold detection circuit concept that uses its offset voltage as the reference threshold and thus directly transforms differential input signal samples into digital values. The use of memristive devices within the design allows us to finely tune the detector's offset voltage, thus ensuring sufficient operational flexibility. Using SPICE simulations we demonstrate an exemplar design built using our concept. First we shown its functionality and then we proceed to examine how: i) mismatch at strategically chosen devices affects the amplifier's offset voltage and ii) changing the resistive state of the memristive devices involved helps the designer control the offset voltage.</p
An analogue-domain, switch-capacitor-based arithmetic-logic unit
No full textThe continuous maturation of novel nanoelectronic devices exhibiting finely tuneable resistive switching is rekindling interest in analogue-domain computation. Regardless of domain, a useful computational module is the arithmetic-logic unit (ALU), which is capable of performing one or more fundamental mathematical operations (typical example: addition and subtraction). In this work we report on a design for an analogue ALU (aAL U) capable of performing barrel addition and subtraction (i.e. ADD/SUB in modular arithmetic). The circuit only requires 5 minimum-size transistors and 1 capacitor. We show that our aALU is in principle capable of handling 5 bits of information using a single input/output wire. Core power dissipation per operation is estimated to peak at ~ 59 f J (input operand-dependent) in TSMC's 65 nm technology.</p
Palimpsest memories stored in memristive synapses
No full textBiological synapses store multiple memories on top of each other in a palimpsest fashion and at different time scales. Palimpsest consolidation is facilitated by the interaction of hidden biochemical processes governing synaptic efficacy during varying lifetimes. This arrangement allows idle memories to be temporarily overwritten without being forgotten, while previously unseen memories are used in the short term. While embedded artificial intelligence can greatly benefit from this functionality, a practical demonstration in hardware is missing. Here, we show how the intrinsic properties of metal-oxide volatile memristors emulate the processes supporting biological palimpsest consolidation. Our memristive synapses exhibit an expanded doubled capacity and protect a consolidated memory while up to hundreds of uncorrelated short-term memories temporarily overwrite it, without requiring specialized instructions. We further demonstrate this technology in the context of visual working memory. This showcases how emerging memory technologies can efficiently expand the capabilities of artificial intelligence hardware toward more generalized learning memories
cgiotis/palimpsest_memories: Dataset and Code Material for "Palimpsest Memories Stored in Memristive Synapses" Manuscript."
No full textDataset and code material for the "Palimpsest Memories Stored in Memristive Synapses" manuscript, currently available on ArXiv. This repository currently contains instructions and the necessary dataset to recreate Figures 1 and 2 from the paper, as well as parametric code to recreate the simulation results and generate the relevant plots (Figures 3 and 4).</span
Resistive switching of Pt/TiO<sub>x</sub>/Pt devices fabricated on flexible Parylene-C substrates
No full textPt/TiOx/Pt resistive switching (RS) devices are considered to be amongst the most promising candidates in memristor family and the technology transfer to flexible substrates could open the way to new opportunities for flexible memory implementations. Hence, an important goal is to achieve a fully flexible RS memory technology. Nonetheless, several fabrication challenges are present and must be solved prior to achieving reliable device fabrication and good electronic performances. Here, we propose a fabrication method for the successful transfer of Pt/TiOx/Pt stack onto flexible Parylene-C substrates. The devices were electrically characterised, exhibiting both digital and analogue memory characteristics, which are obtained by proper adjustment of pulsing schemes during tests. This approach could open new application possibilities of these devices in neuromorphic computing, data processing, implantable sensors and bio-compatible neural interfaces
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