1,721,185 research outputs found
Computing on Knights Architectures (COKA)
No full textCOKA plans to study possible ways to efficiently use up-coming Intel many-core MIC architectures for applications relevant for theoretical physics and for triggering and data-analysis for HEP experiments.
MIC systems, developed as co-processor accelerators, will be available to the mass-market by the end of 2012.
It is now well clear that in the near future performance gains in processing will mainly come from many-core processing architectures; this trend has already emerged in the development of GP-GPUs while massively many core processors (such as the MIC architectures) are forecast for the near future.
For this reason, we consider it important to start to investigate performances of the MIC systems as early as possible, and develop programming methodologies to effectively use all kinds of parallelism available on the processor.
COKA plans to address these issues, investigating the performances of applications relevant both in the fields of theoretical and experimental physics.
For the first class we plan to consider Lattice Boltzmann simulation programs, Monte Carlo simulations of Spin Glass systems, and later Lattice QCD. For the latter, we address applications of data-analysis and trigger computing.
As a final goal we plan to assess if MIC architectures can be used as building blocks to develop massively parallel systems for scientific computing
Computing on Knights Architecture (COKA)
No full textCOKA plans to study possible ways to efficiently use up-coming Intel many-core MIC architectures for applications relevant for theoretical physics and for triggering and data-analysis for HEP experiments. MIC systems, developed as co-processor accelerators, will be available to the mass-market by the end of 2012. It is now well clear that in the near future performance gains in processing will mainly come from many-core processing architectures; this trend has already emerged in the development of GP-GPUs while massively many core processors (such as the MIC architectures) are forecast for the near future. For this reason, we consider it important to start to investigate performances of the MIC systems as early as possible, and develop programming methodologies to effectively use all kinds of parallelism available on the processor. COKA plans to address these issues, investigating the performances of applications relevant both in the fields of theoretical and experimental physics. For the first class we plan to consider Lattice Boltzmann simulation programs, Monte Carlo simulations of Spin Glass systems, and later Lattice QCD. For the latter, we address applications of data-analysis and trigger computing. As a final goal we plan to assess if MIC architectures can be used as building blocks to develop massively parallel systems for scientific computing
Energy-Performance Tradeoffs for HPC Applications on Low Power Processors
No full textEnergy efficiency is becoming more and more important in the HPC field; high-end processors are quickly evolving towards more advanced power-saving and power-monitoring technologies. On the other hand, low-power processors, designed for the mobile market, attract interest in the HPC area for their increasing computing capabilities, competitive pricing and low power consumption. In this work we study energy and computing performances of a Tegra K1 mobile processor using an HPC Lattice Boltzmann application as a benchmark. We run this application on the ARM Cortex-A15 CPU and on the GK20A GPU, both available in this processor. Our analysis uses time-accurate measurements, obtained by a simple custom-developed current monitor. We discuss several energy and performance metrics, interesting per se and also in view of a prospective use of these processors in a HPC context
A Portable OpenCL Lattice Boltzmann Code for Multi- and Many-core Processor Architectures
No full textAbstractThe architecture of high performance computing systems is becoming more and more heterogeneous, as accelerators play an increasingly important role alongside traditional CPUs. Programming heterogeneous systems efficiently is a complex task, that often requires the use of specific programming environments. Programming frameworks supporting codes portable across different high performance architectures have recently appeared, but one must carefully assess the relative costs of portability versus computing efficiency, and find a reasonable tradeoff point. In this paper we address precisely this issue, using as test-bench a Lattice Boltzmann code implemented in OpenCL. We analyze its performance on several different state-of-the-art processors: NVIDIA GPUs and Intel Xeon-Phi many-core accelerators, as well as more traditional Ivy Bridge and Opteron multi-core commodity CPUs. We also compare with results obtained with codes specifically optimized for each of these systems. Our work shows that a properly structured OpenCL code runs on many different systems reaching performance levels close to those obtained by architecture-tuned CUDA or C codes
An FPGA-based Torus Communication Network
No full textWe describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results
AgrUNet: A Multi-GPU UNet Based Model for Crops Classification
No full textAgriculture acts as a catalyst for comprehensive economic growth, boosting income levels, mitigating poverty, and contrasting hunger. For these reasons, it is important to monitor agricultural practices and the use of parcels carefully and automatically to support the development of sustainable use of natural resources. The deployment of high-resolution satellite missions, like LandSat and Copernicus Sentinel, combined with AI Deep Learning (DL) methodologies has revolutionized Earth Observation science, enabling studies on yield predictions, soil classifications, and crop mappings on large areas, and the analysis and processing of Big Data using innovative approaches. This approach requires high-performance computing systems since DL algorithms are known to be very computing-heavy, and recent multi-GPU HPC systems can boost by one or two orders of magnitude the processing power of classical computing systems based only on CPUs. In this study, we develop AgrUNet, a scalable, fast, and reliable UNet-based architecture DL model to perform crop classification on multispectral multitemporal satellite data, implemented and optimized to run on single and multi-GPU HPC systems. Our model achieves a Dice score of approximately 0.90, a peak throughput of 59 and 605 /s for the train and inference steps respectively, improving by approximately a factor 7X the best results reported in the literature and quite ideal speedup running both on a 4X V100 and 8X A100 GPU systems
Energy-Efficiency Evaluation of FPGAs for Floating-Point Intensive Workloads
No full textIn this work we describe a method to measure the computing performance and energy-efficiency to be expected of an FPGA device. The motivation of this work is given by their possible usage as accelerators in the context of floating-point intensive HPC workloads. In fact, FPGA devices in the past were not considered an efficient option to address floating-point intensive computations, but more recently, with the advent of dedicated DSP units and the increased amount of resources in each chip, the interest towards these devices raised. Another obstacle to a wide adoption of FPGAs in the HPC field has been the low level hardware knowledge commonly required to program them, using Hardware Description Languages (HDLs). Also this issue has been recently mitigated by the introduction of higher level programming framework, adopting so called High Level Synthesis approaches, reducing the development time and shortening the gap between the skills required to program FPGAs wrt the skills commonly owned by HPC software developers. In this work we apply the proposed method to estimate the maximum floating-point performance and energy-efficiency of the FPGA embedded in a Xilinx Zynq Ultrascale+ MPSoC hosted on a Trenz board
Optimizing communications in multi-GPU Lattice Boltzmann simulations
No full textAn increasingly large number of scientific applications run on large clusters based on GPU systems. In most cases the large scale parallelism of the applications uses MPI, widely recognized as the de-facto standard for building parallel applications, while several programming languages are used to express the parallelism available in the application and map it onto the parallel resources available on GPUs. Regular grids and stencil codes are used in a subset of these applications, often corresponding to computational 'Grand Challenges'. One such class of applications are Lattice Boltzmann Methods (LB) used in computational fluid dynamics. The regular structure of LB algorithms makes them suitable for processor architectures with a large degree of parallelism like GPUs. Scalability of these applications on large clusters requires a careful design of processor-to-processor data communications, exploiting all possibilities to overlap communication and computation. This paper looks at these issues, considering as a use case a state-of-the-art two-dimensional LB model, that accurately reproduces the thermo-hydrodynamics of a 2D-fluid obeying the equation-of-state of a perfect gas. We study in details the interplay between data organization and data layout, data-communication options and overlapping of communication and computation. We derive partial models of some performance features and compare with experimental results for production-grade codes that we run on a large cluster of GPUs
Evaluation of DVFS techniques on modern HPC processors and accelerators for energy-aware applications
No full textEnergy efficiency is becoming increasingly important for computing systems, in particular for large scale High Performance Computing (HPC) facilities. In this work, we evaluate, from a user perspective, the use of Dynamic Voltage and Frequency Scaling techniques, assisted by the power and energy monitoring capabilities of modern processors to tune applications for energy efficiency. We run selected kernels and a full HPC application on 2 high-end processors widely used in the HPC context, namely, an NVIDIA K80 GPU and an Intel Haswell CPU. We evaluate the available trade-offs between energy-to-solution and time-to-solution, attempting a function-by-function frequency tuning. We finally estimate the benefits obtainable running the full code on an HPC multi-GPU node, with respect to default clock frequency governors. We instrument our code to accurately monitor power consumption and execution time without the need of any additional hardware, and we enable it to change CPUs and GPUs clock frequencies while running. We analyze our results on the different architectures using a simple energy-performance model and derive a number of energy saving strategies, which can be easily adopted on recent high-end HPC systems for generic applications
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