290 research outputs found
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2-D Materials: Low Power Electronics and Novel Device Possibilities
No full text2-D Materials: Low Power Electronics and Novel Device PossibilitiesbyVarun MishraDoctor of Philosophy in Engineering – Electrical Engineering and Computer SciencesUniversity of California, BerkeleyProfessor Sayeef Salahuddin, ChairSemiconductor modeling assumes a critical role in understanding the physics of nanoscale devices as semi-classical approaches start breaking down for highly scaled devices. In this thesis, a quantum transport simulator is designed within the non-equilibrium Greens function (NEGF) formalism to explore the application of layered materials in low-power electronic and novel spintronic devices.The quantum transport simulator is used to calculate the optimal performance of transition metal dichalcogenides (TMD) field effect transistors at the ultimately scaled limit of 5 nm gate lengths. MoS2 based transistors are studied in further detail using a rigorous tight binding Hamiltonian in order to include the effects of non-parabolicity of the electronic structure on the transistor performance. Large band gaps and effective masses were shown to result in excellent switching performance with ON/OFF ratios of 10 5 even at 5 nm gate lengths showing potential applicability in low power electronics, while screening effects were found to affect the drive current in few-layer devices. Possibility of a one-dimensional spin channel is also discussed at the junction of a lateral heterostructure of two dimensional TMDs when the system is in non-equilibrium in the absence of any external magnetic field. The one-dimensional spin channel arises out of spin-orbit splitting in conjunction with the in-plane electric field that exists in the heterojunction of two materials with a conduction band offset. A spin polarization of 0.1 % was calculated at the junction of MoS2 /WSe2 , while the effect of effective mass and spin diffusion on the above is discussed. Such one dimensional spin channel could open up the possibility to probe spin dynamics in confined phase spaces while contributing to spintronics applications
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Design and Characterization of Ferroelectric Negative Capacitance
No full textBecause of the thermal distribution of electrons in a semiconductor, modern transistors cannot be turned on more sharply than 60 mV of gate voltage for an order of magnitude increase in drain current, the so-called ”Boltzmann tyranny.” This results in an inability to reduce supply voltage, increasing power dissipation in advanced complementary metal- oxide-semiconductor (CMOS) technologies, which threatens the continuation of exponential transistor scaling, also known as Moore’s Law. For this reason, there has been a push in the device research community to invent novel steep swing devices. Negative capacitance in ferroelectric materials was proposed in 2008 by Salahuddin and Datta to provide voltage amplification without needing to design a totally new device. A negative gate capacitance would step-up the applied gate voltage at the semiconductor channel, causing the surface potential to rise faster than the gate voltage, lowering the subthreshold slope below 60 mV/decade. In this work, we attempt to characterize the charge-voltage characteristics of ferroelectrics biased into the negative capacitance regime. Although negative capacitance was experimentally demonstrated in 2010, significant challenges have remained to the practical realization of negative capacitance field-effect transistors (FETs).First, we investigate negative capacitance in an isolated ferroelectric capacitor, and show that the negative capacitance states can be directly observed during switching. Careful analysis of the switching dynamics and phase-field modeling show that the signature of negative capacitance arises from the accelerating growth of domain walls, when an increasing volume fraction of the ferroelectric is depolarized. Although this offers insight into the origins of negative capacitance and help to establish its existence scientifically, it does not address the problem of design. A primary concern is the speed of polarization response, which should be on the order of 1 picosecond or less in order to maintain circuit performance. By analyzing the electromagnetic absorption spectrum of hafnium oxide, the primary candidate for CMOS integration, we are able to estimate the intrinsic delay time as being on the order of 270 fs. Next, in order to maximize the amplification and provide adequate margins for hysteresis-free operation, it is necessary to understand how coupling of the ferroelectric material to the interfacial oxide and semiconductor affects its behavior, and to be able to predict what values of negative capacitance will be realized for a certain material and geometry. This is the problem of capacitance matching, which we aim to solve by using the underlying transistor itself as a charge sensor. By calibrating the drain current to the surface potential in reference devices, we may ascertain the characteristics of the ferroelectric in the negative capacitance devices. This is first carried out with an epitaxial ferroelectric capacitor externally connected to the gate of pre-fabricated Fin-FETs. Following this, we describe the development of an in-house fabrication process using silicon-on-insulator substrates, which allows for simple and efficient process flows. Then, we describe the characterization of these devices, including quasistatic and low-frequency current-voltage (I-V) and capacitance voltage (C-V) measurements, a fast pulse-gated I-V measurement, and an excursion into the memory characteristics of our fabricated FETs. Finally, we discuss efforts to build a computational model of our devices from which we can extract the ferroelectric characteristics needed for predictive design
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Negative capacitance and hyperdimensional computing for unconventional low-power computing
No full textProperties that emerge from the collective behavior of constituents at different length scales can be exploited to reduce power consumption below conventional limits in computing. At the device level, ferroelectric-dielectric coupling ("negative capacitance") can reduce energy consumption below 1 / 2 CV^2 in capacitors. However, this effect is still not well understood. We construct a microscopic model and analyze energy flow from the perspective of Poynting’s theorem to clear up these misunderstandings. At the circuit level, high-dimensional distributed representations relax requirements on signal-to-noise ratio and supply voltage, and enable new architecture designs. Computing with these representations ("hyperdimensional computing") is natural for performing energy efficient cognitive computing at the application level. However, data in practice is always measured in some sort of representation, which may not be natural for hyperdimensional computing. We bridge this gap by proposing to use an approximation of the bispectrum to map data measured in practice into high-dimensional distributed representations for use with hyperdimensional computing
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Negative Capacitance for Ultra-low Power Computing
No full textOwing to the fundamental physics of the Boltzmann distribution, the ever-increasing power dissipation in nanoscale transistors threatens an end to the almost-four-decade-old cadence of continued performance improvement in complementary metal-oxide-semiconductor (CMOS) technology. It is now agreed that the introduction of new physics into the operation of field-effect transistors--in other words, ``reinventing the transistor''-- is required to avert such a bottleneck. In this dissertation, we present the experimental demonstration of a novel physical phenomenon, called the negative capacitance effect in ferroelectric oxides, which could dramatically reduce power dissipation in nanoscale transistors. It was theoretically proposed in 2008 that by introducing a ferroelectric negative capacitance material into the gate oxide of a metal-oxide-semiconductor field-effect transistor (MOSFET), the subthreshold slope could be reduced below the fundamental Boltzmann limit of 60 mV/dec, which, in turn, could arbitrarily lower the power supply voltage and the power dissipation. The research presented in this dissertation establishes the theoretical concept of ferroelectric negative capacitance as an experimentally verified fact. \\The main results presented in this dissertation are threefold. To start, we present the first direct measurement of negative capacitance in isolated, single crystalline, epitaxially grown thin film capacitors of ferroelectric Pb(ZrTi)O. By constructing a simple resistor-ferroelectric capacitor series circuit, we show that, during ferroelectric switching, the ferroelectric voltage decreases, while the stored charge in it increases, which directly shows a negative slope in the charge-voltage characteristics of a ferroelectric capacitor. Such a situation is completely opposite to what would be observed in a regular resistor-positive capacitor series circuit. This measurement could serve as a canonical test for negative capacitance in any novel material system. Secondly, in epitaxially grown ferroelectric Pb(ZrTi)O-dielectric SrTiO heterostructure capacitors, we show that negative capacitance effect from the ferroelectric Pb(ZrTi)O layer could result in an enhancement of the capacitance of bilayer heterostructure over that of the constituent dielectric SrTiO layer. This observation apparently violates the fundamental law of circuit theory which states that the equivalent capacitance of two capacitors connected in series is smaller than that of each of the constituent capacitors. Finally, we present a design framework for negative capacitance field-effect-transistors and project performance for such devices
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Switching Dynamics of Thin Film Ferroelectric Devices- A Massively Parallel Phase Field Study
No full textIn this thesis, we investigate the switching dynamics in thin film ferroelectrics. Ferroelectric materials are of inherent interest for low power and multi-functional devices. However, possible device applications of these materials have been limited due to the poorly understood electromagnetic and mechanical response at the nanoscale in arbitrary device structures. The difficulty in understanding switching dynamics mainly arises from the presence of features at multiple length scales and the nonlinearity associated with the strongly coupled states. For example, in a ferroelectric material, the domain walls are of nm size whereas the domain pattern forms at micron scale. The switching is determined by coupled chemical, electrostatic, mechanical and thermal interactions. Thus computational understanding of switching dynamics in thin film ferroelectrics and a direct comparison with experiment poses a significant numerical challenge. We have developed a phase field model that describes the physics of polarization dynamics at the microscopic scale. A number of efficient numerical methods have been applied for achieving massive parallelization of all the calculation steps. Conformally mapped elements, node wise assembly and prevention of dynamic loading minimized the communication between processors and increased the parallelization efficiency. With these improvements, we have reached the experimental scale - a significant step forward compared to the state of the art thin film ferroelectric switching dynamics models. Using this model, we elucidated the switching dynamics on multiple surfaces of the multiferroic material BFO. We also calculated the switching energy of scaled BFO islands. Finally, we studied the interaction of domain wall propagation with misfit dislocations in the thin film. We believe that the model will be useful in understanding the switching dynamics in many different experimental setups incorporating thin film ferroelectrics
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Tunneling in low-power device-design: A bottom-up view of issues, challenges, and opportunities
No full textSimulation of electronic transport in nanoscale devices plays a pivotal role in shedding light on underlying physics, and in guiding device-design and optimization. The length scale of the problem and the physical mechanism of device operation guide the choice of formalism. In the sub-20 nanometer regime, semi-classical approaches start breaking down, thus necessitating a quantum-mechanical treatment of the electronic transport problem. Non-equilibrium Green's function (NEGF) is a theoretical framework for investigating quantum-mechanical systems - interacting with surroundings through exchange of quasiparticles - far from equilibrium. Although hugely computation-intensive with a realistic device-representation, it provides a rigorous way to include particle-particle interactions and to model phenomena that are inherently quantum-mechanical.We build the Berkeley Quantum Transport Simulator (BQTS) - a massively parallel, generic, NEGF-based numerical simulator - to explore low-power device-design opportunities. Demonstrating scalability and benchmarking results with experimental tunnel diode data, we set out to understand tunneling in devices and to leverage it for both digital and analog applications. Investigating InAs short-channel band-to-band tunneling transistors (TFETs), we show that direct source-to-drain tunneling sets the leakage-floor in such devices, thereby limiting the minimum subthreshold swing (SS) in spite of excellent electrostatics. A heterojunction TFET with a halo doping in the source-channel overlap region is proposed and is shown to achieve steep SS as well as large ON current. We discover that by band-offset engineering, the steepness therein could be controlled primarily by the modulation of heterojunction-barrier. Subsequently, exploring layered materials for analog applications, we demonstrate that doping the drain underlap region in graphene FETs prolongs the onset of tunneling in their output characteristics, and hence significantly increases their output resistance (r0) and intrinsic gain (gmr0). Due to large bandgap, and consequently, large r0, monolayer-MoS2 FETs exhibit a significant enhancement in maximum oscillation frequency (fmax) over their graphene counterparts
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Quantum Transport and Phase-Field Modeling for Next-Generation Logic Devices
No full textModeling of semiconductor devices plays an important role in determining which future technologies are most promising for the semiconductor industry as well as optimizing the performance and better understanding the underlying physics of existing devices. This thesis focuses on the design, development, and use of software to study transport in low-dimensional materials and explores the physics of negative capacitance in ferroelectrics.Quantum transport simulation is used to examine the properties of graphene nanoribbons in geometries that can be fabricated through bottom-up chemical synthesis. The chevron graphene nanoribbon is shown to have an electronic structure analogous to traditional semiconductor superlattices. It is shown how this property could be utilized to create a new type of device, which exhibits both negative differential resistance and steep-slope (< 60 mV/decade) switching for low-power electronics applications. We discuss BerkeleyNano3D, a new quantum transport simulator based on the non-equilibrium Green’s function (NEGF) formalism, which is capable of efficient three-dimensional device simulation on large computing clusters.Finally, the phenomenon of ferroelectric negative capacitance is examined through the lens of phase-field simulations based on the time-dependent Ginzburg-Landau equation. This phenomenon has been previously predicted as a means to enable energy-efficient steep-slope device with minimal modification to existing transistor processes. Simulation results from three-dimensional phase-field modeling provide new insight into the underlying mechanisms for negative capacitance and give far better agreement with experiment than previously studied single domain models
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Modeling and Design of Nanoscale Ferroelectric and Negative-Capacitance Gate Transistors
No full textIntegration of Hf-based ferroelectric materials into the MOSFET gate stack introduces new physics that potentially enables continued scaling for both CMOS and memory devices. The electrostatic potential amplification effect arises when the device is engineered to depolarize and hence stabilize the ferroelectric negative capacitance state, which eliminates the ferroelectric hysteresis and enhances the gate control. On the other hand, when the ferroelectric layer is thick enough to overcome the depolarization field, non-volatile memory function can be realized through the remnant polarization states. Such systems exhibit process and structural compatibility with CMOS technology and thus are of significant application relevance. Experiments have demonstrated low-voltage operations for both types of devices, showing promising prospects for next-generation logic devices with high reliability.To harness the effects for designing the NCFET and FeFET devices, it is important to understand the behaviours of the ferroelectric layer in the relevant states. In this dissertation, the polarization responses of negative capacitance states are modeled from different aspects through self-consistent device and circuit models that are calibrated to experimental measurements. First, the 101-stage ring oscillator consisting of 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance are used to study the response speed of the negative capacitance effect. The consistency of the device DC characteristics and the circuit oscillations with less than 10ps per-stage delay confirm the fast negative capacitance response. Next, NCFET device characteristics and scaling trends that are unexpected by conventional theory were explained with non-linear negative capacitance responses as described by the Landau's phenomenology. Design insights are drawn, and the observation bodes well for extending the MOSFET gate length scaling limit. Finally, high-speed NCFET RF operations are projected and designed based on experimental characterization results and Monte-Carlo transport simulations. Silicon-channel NCFETs are expected to achieve cutoff frequency over 400GHz with standard SOI device structures and over 650GHz with air-gap spacers.The carrier dynamics of memory program and readout operations for an n-type SOI FeFET are studied through TCAD simulations. Gate-induced drain leakages during the program operation with large negative gate biases can result in excessive hole concentrations with lifetime exceeding microseconds during the hold phase. While the excess holes result in approximately 100ps delay in the readout phase before a large read margin can be detected, it benefits the program speed and the quasi-steady-state read margin. Therefore, such effects can be utilized for low-power memory applications through proper SOI FeFET designs with the awareness of excess carrier dynamics
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HfO2-ZrO2-based Ferroelectricity for Next-Generation Energy-Efficient Electronics
No full textOver the past few decades, data generation from diverse sources, including the Internet of Things (IoT) and artificial intelligence (AI) applications, has grown exponentially. This surge in data has driven an unprecedented demand for hardware capable of supporting the extensive information processing required today. Consequently, the energy consumption of microelectronics has risen sharply and is projected to exceed 20% of global energy production by 2030. Addressing this challenge requires groundbreaking advances in materials and devices to develop more energy-efficient electronics. Ferroelectric materials, along with the negative capacitance effect, present a promising platform for achieving energy-efficient computing, memory, and energy storage solutions. The recent discovery of ferroelectricity in hafnium oxide (HfO2)-based systems—compatible with modern semiconductor fabrication processes—has rekindled interest in integrating ferroelectrics into current technologies.In this dissertation, I integrate CMOS-compatible HfO2-ZrO2-based ferroelectrics within device structures designed towards realizing this goal. First, I demonstrate ultrathin (anti)ferroelectric stabilization in HfO2-ZrO2 films down to unit-cell thickness, showing the absence of a critical ferroelectric thickness in this material system. Next, I integrate ultrathin HfO2-basedferroelectrics into ferroelectric tunnel junctions (FTJs) toward achieving an embedded nonvolatile memory. I next investigate negative capacitance stabilization in ultrathin HfO2-ZrO2 heterostructures as a novel approach to equivalent oxide thickness (EOT) scaling in transistors, enabling further reductions in operating voltage beyond conventional high-κ dielectrics.
Lastly, I demonstrate the negative capacitance effect in HfO2-ZrO2-Al2O3 superlattices, which, when integrated into 3D trench capacitors, achieve record-high energy and power densities for electrostatic energy storage. The breakthroughs presented in this work—ultrathin ferroelectricity and negative capacitance—within the CMOS-compatible HfO2-ZrO2 material system pave a new path toward energy-efficient electronics. These advancements highlight the potential for innovative material integration to address the increasing energy demands of modern computing technologies
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