1,354,217 research outputs found
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits
No full textLeakage power has become a serious concern in nanometer CMOS technologies, and power-gating has shown to offer a viable solution to the problem with a small penalty in performance. This paper focuses on leakage power reduction through automatic insertion of sleep transistors for power-gating. In particular, we propose a novel, layout-aware methodology that facilitates sleep transistor insertion and virtual-ground routing on row-based layouts. We also introduce a clustering algorithm that is able to handle simultaneously timing and area constraints, and we extend it to the case of multi- Vt sleep transistors to increase leakage savings. The results we have obtained on a set of benchmark circuits show that the leakage savings we can achieve are, by far, superior to those obtained using existing power-gating solutions and with much tighter timing and area constraints
Row-based FBB: A design-time optimization for post-silicon tunable circuits
No full textCircuit variabilityhasadverseconsequencesondesignpredictabilityandyieldinNanometerCMOS.
Post-fabricationtuningapproacheshavebeentargetedinanumberofrecentworkstomitigatethis
problem.AdaptiveBodyBias(ABB)isoneofthemostsuccessfultuningknobsinusetodayinhigh-
performancecustomdesign.Throughforwardbodybias(FBB),thethresholdvoltageoftheCMOS
devices canbereducedafterfabricationtobringtheslowdiesbackwithintherangeofacceptable
specs. FBBisusuallyappliedwithaverycoarsegranularityatthepriceofasignificantlyincreased
leakagepower.Weproposeanovel,fine-grainedFBBschemeonrow-basedstandardcelllayoutthat
enablesselectiveforwardbodybiasingofthoserowsthatcontainmosttimingcriticalgates,thereby
reducingleakagepoweroverhead.Thisstyleisfullycompatiblewithstate-of-the-artcommercial
physicaldesignflowsandimposesminimalareablow-up.Itcanbeappliedwithoutanyplacement
disruptiononafullyplaceddesign.Benchmarkresultsshowlargeleakagepowersavingswitha
maximumsavingsof61%incaseof18%compensationin45nmand93%incaseof10%compensation
in 32nmwithrespecttoblock-levelapproache
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew
No full textPower densities and temperatures in today's high performance circuits have reached alarmingly high levels due to increased scaling in feature sizes. Subsequently, the various techniques used to keep them under control have also created "zones" of varying temperatures, thus contributing to temperature gradients inside the chip. These gradients have detrimental effects on the delay of wires, as resistance in metals increases with temperature. Clock nets are extremely susceptible to this effect, since they run through the entire chip. Different techniques have been proposed to counter the impact of temperature on clock speed; they range from re-designing the clock network assuming a stationary profile to more adaptive solutions that allow to dynamically compensate the clock skew through replacement of the original buffers with a specially designed counterpart, called tunable delay buffers (TDBs). Dynamic skew management based on TDBs calls for the presence on the chip of a thermal management unit (TMU), whose purpose is that of periodically choosing the actual delay that each TDB must provide in order to achieve skew optimization. Preliminary implementations of such a unit for basic assumptions on the distribution of sensors and their accuracy have indicated negligible impact on the original design. This work aims at exploring in detail several issues related to TMU design, pivoting on the fact that sensor distribution and its accuracy could in fact impact the design in a significant way depending on the design. We provide the results of a careful exploration we have performed on a meaningful case study, quantifying values for area and power consumptio
A Scalable Algorithmic Framework for Row-Based Power-Gating
No full textLeakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in standard cell based designs. In particular, we propose clustering algorithms for row-based power-gating methodology which is based on using rows of the layout as the granularity for clustering. Our clustering methodology does timing and area constraint driven power-gating in contrast to only timing driven power-gating as proposed in the previous works. We present two distinct clustering algorithms with different accuracy-efficiency trade-off. An optimal one, which exploits a 0-1 or Binary Integer Programming approach, and a heuristic one, which resorts to an implicit enumeration of the layout rows. Results show that, for all the benchmarks, the leakage power savings, as compared to previous techniques, are more than 75% when we have the same timing constraints but half sleep transistor area and at least 60% when area constraint is set at one fourth. We also show that we can perform clustering with no speed degradation and achieve maximum leakage power savings up-to 83
Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating
No full textTemporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating
No full textThe use of sleep transistors as power-gating elements to cut-off sub-threshold leakage stand-by currents has become a very popular solution to tackle the rise of leakage energy consumption in nano-CMOS designs. One of the most critical challenges in sleep-transistor based power gating is the sizing of the sleep transistor, which mainly depends on the discharge current pattern over time of the set of cells that share a single sleep transistor.
In this work we provide a sleep transistor clustering and sizing methodology that improves over previous solutions by (i) accounting for sleep transistor area constraints (thus implying the possibility of gating only a subset of the cells of the design), and (ii) by utilizing the temporal variations in discharge current pattern to achieve improved leakage power-savings. Experimental results on standard benchmarks show that we can achieve improvement in leakage power savings, compared to previous works, ranging from 12% to 17% on average, depending on the allowed area constraint
Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers
No full textThe thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular by increasing the skew of the clock net and/or altering hold/setup constraints, possibly causing the circuit to operate incorrectly. The knowledge of the spatial distribution of temperature can be used to properly design a clock network that is able to compensate such thermal non-uniformities. However, re-design of the clock network is effective only if temperature distribution is stationary, i.e., does not change over time. In this work, we specifically address the problem of dynamically modifying the clock tree in such a way that it can compensate for temporal variations of temperature. This is achieved by exploiting the buffers that are inserted during the clock network generation, by transforming them into tunable delay elements. Temperature-induced delay variations are then compensated by applying the proper tuning to the tunable buffers, which is computed off-line and stored in a tuning table inserted in the design. We propose an algorithm to minimize the number of inserted tunable buffers, as well as their tunable range (which directly relates to complexity). Results show that clock skew is kept within original bounds with minimum area and power penalty. The maximum increase in power is 23.2% with most benchmarks exhibiting less than 5% increase in power
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology
No full textClustered sleep transistor insertion is an effective leakage power reduction technique that is well-suited for integration in an automated design flow and offers a flexible tradeoff between area, delay overhead and turn-on transition time. In this work, we focus on the design of a family of sleep transistor cells, fully compatible with the physical design rules of a commercial 65nm CMOS library. We describe circuit-level and layout optimizations, as well as the cell characterization procedure required to support automated sleep transistor cell selection and instantiation in a clustered power-gating insertion flo
Optimal sleep transistor synthesis under timing and area constraints
No full textLeakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and industry. Many techniques have been proposed in the literature for leakage power reduction and one of the prominent techniques for leakage power reduction is the use of sleep transistors as power-gating elements to cut-off sub-threshold leakage current in circuits when they are in stand-by mode. Although sleep transistor insertion is very effective in cutting-off leakage, it also incurs timing, area and routing overhead. Since most of the sleep transistor insertion methodologies do post layout insertion, care should be taken such that there is minimal perturbation of the original layout. Over design of sleep transistors cells and sub-optimal sleep transistor placement must be avoided to achieve final design closure. Since the sleep transistor area plays an important and prominent role in this aspect, it necessitates for optimal sleep transistor sizing and synthesis technique under area constraints. In this paper, we first provide a methodology for optimal sleep transistor synthesis under given area constraints. We then apply our technique to the general timing and area constraint driven row-based power-gating methodology proposed in [13] and show how optimal low leakage designs with constraints on timing and area can be designe
Automatic synthesis of near-threshold circuits with fine-grained performance tunability
No full textNear-Threshold Circuits achieve ultra-low energy operating with significant performance improvement and noise immunity as compared to sub-threshold circuits. However, near-threshold circuit performance is highly sensitive to static and dynamic threshold voltage variations. This makes designing circuits for a target performance very difficult, and post-silicon tunability is required to achieve performance targets without taking huge design margins. In this work, we tackle this problem by proposing a novel dual-Vdd technique for near-threshold operation and show that one can tune the performance of a circuit in a fine-grained manner by powering an optimal sub-set of rows with a slightly higher supply voltage than the rest, without incurring the large cost of distributed level shifters. By varying the percentage of rows at a slightly higher voltage, one can trade-off performance and power in a fine-grained manner. Experimental results show that by employing our dual-Vdd technique, we can improve the performance of several benchmarks up-to 45% while achieving more than 50% lower power as compared to single-Vdd implementations
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