348 research outputs found
Digital design techniques for dependable High-Performance Computing
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Micro Latch-up Analysis on Ultra- Nanometer VLSI Technologies: A new Monte Carlo Approach
No full textUltra-scale devices based on technologies below 20nm are nowadays widely adopted due to their elevated computing features and low power consumption. These characteristics made them attractive even for fields where the high reliability is the major concern like automotive or aerospace ones. In order to guarantee a high reliability level, one of the major challenge in these application fields is the protection versus the micro latch-up effect: a phenomenon that temporarily affects the logical behavior of technology cells at various locations across the die provoking circuit misbehavior. In this paper, we propose a new analysis flow for detecting the occurrences of micro latch-up event considering the physical layout of a circuit. In details, a circuit layers has been developed in order to identify the micro latch-up sensitive points in the 3D layout geometry, while a Monte-Carlo approach has been developed to calculate the micro latch-up error rate on routing interconnection nodes. Experimental results have been performed by fault simulation on a benchmark circuit implemented in six different variants of routing congestion using a 15 nm COTS technology library demonstrating the feasibility of the proposed approach
Effective Characterization of Radiation-induced SET on Flash-based FPGAs
No full textSingle Event Transients (SETs) are one of the major concern for Flash-based Field Programmable Gate Arrays (FPGAs). In this paper, we propose a new analysis to characterize the SET phenomena within Flash-based FPGAs
Concurrent Detection and Classification of Faults in Matrix Converter using Trans-Conductance
No full textThis paper presents a fault diagnostic algorithm for detecting and locating open-circuit and short-circiut faults in switching components of matrix converters (MCs) which can be effectively used to drive a permanent magnet synchronous motor for research in critical applications. The proposed method is based on monitoring the voltages and currents of the switches. These measurements are used to evaluate the forward trans-conductance of each transistor for different values of switch voltages. These trans-conductance values are then compared to the nominal values. Under healthy conditions, the values obtained for the fault signal is less than the tolerable value. Under the open/short-circuit conditions, the fault signal exceeds the threshold, hence enables the matrix converter drive to detect and exactly identify the location of the faulty IGBT. The main advantages of this diagnostic method include fast detection and locating of the faulty IGBT, easiness of implementation and independency of the modulation strategy of the converter.DOI: http://dx.doi.org/10.11591/ijpeds.v5i1.606
Digital Design Techniques for Dependable High Performance Computing
No full textAs today’s process technologies continuously scale down, circuits become increasingly more vulnerable to radiation-induced soft errors in nanoscale VLSI technologies. The reduction of node capacitance and supply voltages coupled with increasingly denser chips are raising soft error rates and making them an important design issue. This research work is focused on the development of design techniques for high-reliability modern VLSI technologies, focusing mainly on Radiation-induced Single Event Transient. In this work, we evaluate the complete life-cycle of the SET pulse from the generation to the mitigation. A new simulation tool, Rad-Ray, has been developed to simulate and model the passage of heavy ion into the silicon matter of modern Integrated Circuit and predict the transient voltage pulse taking into account the physical description of the design. An analysis and mitigation tool has been developed to evaluate the propagation of the predicted SET pulses within the circuit and apply a selective mitigation technique to the sensitive nodes of the circuit. The analysis and mitigation tools have been applied to many industrial projects as well as the EUCLID space mission project, including more than ten modules. The obtained results demonstrated the effectiveness of the proposed tools
Radiation-induced SET on Flash-based FPGAs: Analysis and Filtering methods
No full textReliability of Integrated Circuits (ICs) it is nowadays a major concern for deep sub-micron technology. The progressive decreasing of device feature sizes provokes an increasing sensitiveness to radiation-induced particle strikes within the device silicon structure generating a larger number of Single Event Transients (SETs). In the present paper, we propose a new analysis to characterize the SET phenomena within Flashbased FPGAs. Besides, we developed a new mitigation strategy based on the modification of the place and routed design to improve the filtering capability selectively adding electrical resistive capacitive loads without introducing performance degradation and introducing a limited overhead in terms of routing segments. Experimental results performed on a various set of benchmark circuits shows a mitigation of SET improved of 3 orders of magnitude with respect to traditional logical filtering solutions with a minimal performance degradation of about 9%
Radiation-induced single event transients modeling and testing on nanometric flash-based technologies
No full textThe increasing technology node scaling makes VLSI devices extremely vulnerable to Single Event Effects (SEEs) induced by highly charged particles such as heavy ions, increasing the sensitivity to Single Event Transients (SETs). In this paper, we describe a new methodology combining an analytical and oriented model for analyzing the sensitivity of SET nanometric technologies. The paper includes radiation test experiments performed on Flash-based FPGAs using heavy ions radiation beam. Experimental results are detailed and commented demonstrating the effective mitigation capabilities thanks to the adoption of the developed mode
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Kaufvertragsstörungen aus Sicht des BGB und des iranischen Rechts ::Das Wirtschaftsembargo gegen den Iran /
No full textSarah Roja Azimi untersucht die Rechtsgrundlagen und die Modalitäten von Vertragsstörungen bei internationalen Handelsgeschäften, genauer die Störung des Warenexports von Deutschland in den Iran durch ein Wirtschaftsembargo. Sie geht der Frage nach, wie die beiden sehr unterschiedlichen Rechtssysteme mit den Sanktionen umgehen, bzw. welche Auswirkungen die Sanktionen auf Kaufverträge zwischen iranischen und deutschen Geschäftspartnern haben. Die Autorin setzt dies in Beziehung zum iranischen Rechtssystem, um die in der Islamischen Republik Iran inhärenten Widersprüche aufzudecken bzw. die Frage zu klären, inwieweit die Scharia Einfluss auf das iranische Recht hat. Der Inhalt · Internationale handelsrechtliche Regularien · Begriff der Scharia · Die Islamische Republik Iran und das Verhältnis des Rechtssystems zur Scharia · Vertragsstörungen und die Folgen nach deutschem Recht (vor und nach Inkrafttreten eines Embargos) · Vertragsstörungen und die Folgen nach iranischem Recht (Auswirkungen von Wirtschaftssanktionen im iranischen Rechtssystem) Die Zielgruppen · Dozierende und Studierende der Rechtswissenschaften, der Wirtschaftswissenschaften, der Islamwissenschaften · Fach- und Führungskräfte aus dem Handel und Export/Import Die Autorin Dr. Sarah Roja Azimi war wissenschaftliche Mitarbeiterin an der Leuphana Universität, Professional School & Law School, Lüneburg
Evaluation of transient errors in GPGPUs for safety critical applications: An effective simulation-based fault injection environment
No full textGeneral Purpose Graphics Processing Units (GPGPUs) are increasingly adopted thanks to their high computational capabilities. GPGPUs are preferable to CPUs for a large range of computationally intensive applications, not necessarily related to computer graphics. Within the high performance computing context, GPGPUs must require a large amount of resources and have plenty execution units. GPGPUs are becoming attractive for safety-critical applications where the phenomenon of transient errors is a major concern. In this paper we propose a novel transient error fault injection simulation methodology for the accurate simulation of GPGPUs applications during the occurrence of transient errors. The developed environment allows to inject transient errors within all the memory area of GPGPUs and into not user-accessible resources such as in streaming processors combinational logic and sequential elements. The capability of the fault injection simulation platform has been evaluated testing three benchmark applications including mitigation approaches such as Duplication With Comparison, Triple Modular Redundancy and Algorithm Based Fault Tolerance. The amount of computational costs and time measured is minimal thus enabling the usage of the developed approach for effective transient errors evaluation
Reliability evaluation of heterogeneous systems-on-chip for automotive ECUs
No full textAutomotive systems embed an increasing number of heterogeneous devices and architectures that lead the effective reliability analysis a major challenge. With the advent of integrated Virtual Environment, complex system design and simulation have been made possible thanks to the integration of various simulator engines within a unique development platform. In this paper we develop a Fault Injection tool able to inject Single Event Upsets (SEUs) using a Virtual Prototype simulation environment. The developed method results powerful and effective to observe the overall system dependability and characterize the fault tolerance capability of any type of SW/HW module included in the system. Experimental results obtained with an analysis of a gear-shift automotive application demonstrated the feasibility of the developed method
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