1,721,130 research outputs found
Noise Analysis of Submicron Radiation Hardened PMOS NWELL Devices
No full textThe effect, on device parameters, of reverse biasing the bulk to source junction of PMOS-NWELL radiation hardened devices has been carefully analysed before and after irradiation up to 5 Mrad with a 60Co γ-rays source. The transistors, parts of a 0.8μm CMOS process, feature 2500μm gate width and different gate lengths. A sizeable white noise reduction is due to both a reduction of the bulk spreading resistor thermal noise contribution and of the F coefficient
A bond-wire inductor-MOS varactor VCO tunable from 1.8 to 2.4 GHz
No full textThis paper presents a technique that optimizes LC-tank CMOS voltage-controlled oscillators (VCOs) by minimizing the product of phase noise and power consumption. Moreover, it shows that the minimum depends on the tank's quality factor Q, the device noise coefficient γ, and the ratio between the maximum oscillation amplitude and supply voltage α. Prototypes, realized in a 0.35-μm process, show the following performances: -122.5 dBc/Hz at 600 kHz from a 1.9-GHz carrier, with 2-V supply voltage and 1-mA current consumption. The VCO can be tuned between 1.8-2.4 GHz, when the varactor control voltage is varied between 0-3.5 V. In the proposed realization, the tank is made of a metal-oxide-silicon varactor (operated between accumulation and deep depletion) and a bond-wire inductor, realized connecting two pads to a package frame lead to be compatible with the production environmen
Analysis and optimization of IIP2 in CMOS direct down-converters
Full text linkTwo mechanisms are responsible for second order intermodulation in CMOS down-converters: RF self-mixing and device non-linearity and mismatches. An intuitive model and analytical expressions are provided for both of them. A down-converter prototype, drawing 3.2 mA from a 1.8 V supply, part of a fully integrated 0.18 μm CMOS UMTS receiver front-end shows 66 dBm IIP2 and 16 dBm IIP3
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