410 research outputs found
Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS
No full textIncreasing the energy efficiency of deep learning systems is critical for improving the cognitive capability of edge devices, often battery operated, as well as for data centers, constrained by the total power envelope. Specialized architectures accelerated by analog vector-matrix multipliers (VMMs) can reduce by orders of magnitude the energy per operation, since the reduced precision of analog computation does not undermine the classification accuracy of the neural network. We show an analog vector-matrix multiplier fabricated with industry-standard 0.18 μm CMOS process, exploiting a single-transistor non-volatile analog memory cell and dedicated technology circuit co-design. The design is focused on implementation in neural networks performing offline training. The VMM performs the analog multiplication of a vector of inputs, encoded in the duration of time pulses, times a matrix of weights, encoded in the programmable currents of the memory cells. A 1.72 μm2 memory cell is realized with a single transistor with floating gate, which can be operated as a two-terminal analog memristive device with more than 64 programmable current levels and high Ihigh/Ilow ratio (> 10 3 ), tuned by the charge injected in the floating gate. A small-area charge amplifier is used to convert the multiply and accumulate operation result into a voltage. System-level projections based on our measurements and simulations provide a throughput of 333.17 GOps/s and an energy efficiency of 122.3 TOps/J, higher than comparable-precision VMMs reported in the literature, and an equivalent area per cell down to 2.15 μm2 , lower than any similar state-of-the-art solution. Of critical importance in view of translation to industry, our proposal uses in a new way an industry-standard low-cost single-poly CMOS process flow
Assessment of Two-Dimensional Materials-based technology for Analog Neural Networks
No full textEmbedding advanced cognitive capabilities in battery-constrained edge devices requires specialized hardware with new circuit architecture and – in the medium/long term - new device technology. We evaluate the potential of recently investigated devices based on 2D materials for the realization of analog deep neural networks, by comparing the performance of neural networks based on the same circuit architecture using three different device technologies for transistors and analog memories. As a reference result, it is included in the comparison also an implementation on a standard 0.18 μm CMOS technology. Our architecture of choice makes use of current-mode analog vector-matrix multipliers based on programmable current mirrors consisting of transistors and floating-gate non-volatile memories. We consider experimentally demonstrated transistors and memories based on a monolayer Molibdenum Disulfide channel and ideal devices based on heterostructures of multilayer-monolayer PtSe2. Following a consistent methodology for device-circuit co-design and optimization, we estimate layout area, energy efficiency and throughput as a function of the equivalent number of bits (ENOB), which is strictly correlated to classification accuracy. System-level tradeoffs are apparent: for a small ENOB experimental MoS2 floating-gate devices are already very promising; in our comparison a larger ENOB (7 bits) is only achieved with CMOS, signaling the necessity to improve linearity and electrostatics of devices with 2D materials
Power Electronics Based on Wide-Bandgap Semiconductors: Opportunities and Challenges
No full textThe expansion of the electric vehicle market is driving the request for efficient and reliable power electronic systems for electric energy conversion and processing. The efficiency, size, and cost of a power system is strongly related to the performance of power semiconductor devices, where massive industrial investments and intense research efforts are being devoted to new wide bandgap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN). The electrical and thermal properties of SiC and GaN enable the fabrication of semiconductor power devices with performance well beyond the limits of silicon. However, a massive migration of the power electronics industry towards WBG materials can be obtained only once the corresponding fabrication technology reaches a sufficient maturity and a competitive cost. In this paper, we present a perspective of power electronics based on WBG semiconductors, from fundamental material characteristics of SiC and GaN to their potential impacts on the power semiconductor device market. Some application cases are also presented, with specific benchmarks against a corresponding implementation realized with silicon devices, focusing on both achievable performance and system cost
Analog Vector-Matrix Multiplier Based on Programmable Current Mirrors for Neural Network Integrated Circuits
No full textWe propose a CMOS Analog Vector-Matrix Multiplier for Deep Neural Networks, implemented in a standard single-poly 180 nm CMOS technology. The learning weights are stored in analog floating-gate memory cells embedded in current mirrors implementing the multiplication operations. We experimentally verify the analog storage capability of designed single-poly floating-gate cells, the accuracy of the multiplying function of proposed tunable current mirrors, and the effective number of bits of the analog operation. We perform system-level simulations to show that an analog deep neural network based on the proposed vector-matrix multiplier can achieve an inference accuracy comparable to digital solutions with an energy efficiency of 26.4 TOPs/J, a layer latency close to 100 mu s and an intrinsically high degree of parallelism. Our proposed design has also a cost advantage, considering that it can be implemented in a standard single-poly CMOS process flow
12-bit Delta-Sigma ADC Operating at a Temperature of Up to 250 °C in Standard 0.18 μm SOI CMOS
No full textSome applications require electronic systems to operate at extremely high temperature. Extending the operating temperature range of automotive-grade CMOS processes - through the use of dedicated design techniques - can provide an important cost-effective advantage. We present a second-order discrete-time delta-sigma analog-to-digital converter operating at a temperature of up to 250° C, well beyond the 175°C qualification temperature of the automotive-grade CMOS process used for its fabrication (XFAB XT018). The analog-to-digital converter incorporates design techniques that are effective in mitigating the adverse effects of the high temperature, such as increased leakage currents and electromigration. We use configurations of dummy transistors for leakage compensation, clock-boosting methods to limit pass-gate cross-talk, and we optimized the circuit architecture to ensure stability and accuracy at high temperature. Comprehensive measurements demonstrate that the analog-to-digital converter achieves a signal-to-noise ratio exceeding 93 dB at 250°C over a signal bandwidth of 146 Hz, with an effective number of bits of 12, and a power consumption of only 44 mW. The die area of the converter is only 0.065 mm2 and the area overhead of the high-temperature mitigation circuits is only 13.7%. The Schreier Figure of Merit is 140 dB at the maximum temperature of 250°C, proving the potential of the circuit for reliable operation in challenging applications such as gas and oil extraction and aeronautics
Temperature-Resilient Analog Neuromorphic Chip in Single-Polysilicon CMOS Technology
No full textIn analog neuromorphic chips, designers can embed computing primitives in the intrinsic physical properties of devices and circuits, heavily reducing device count and energy consumption, and enabling high parallelism, because all devices are computing simultaneously. Neural network parameters can be stored in local analog non-volatile memories (NVMs), saving the energy required to move data between memory and logic. However, the main drawback of analog sub-threshold electronic circuits is their dramatic temperature sensitivity. In this paper, we demonstrate that a temperature compensation mechanism can be devised to solve this problem. We have designed and fabricated a chip implementing a two-layer analog neural network trained to classify low-resolution images of handwritten digits with a low-cost single-poly complementary metal-oxide-semiconductor (CMOS) process, using unconventional analog NVMs for weight storage. We demonstrate a temperature-resilient analog neuromorphic chip for image recognition operating between 10°C and 60°C without loss of classification accuracy, within 2% of the corresponding software-based neural network in the whole temperature range
A 6.78 MHz Maximum Efficiency Tracking Active Rectifier with Load Modulation Control for Wireless Power Transfer to Implantable Medical Devices
No full textThis paper presents a novel integrated wireless power transfer receiver for implantable medical devices, including a load-modulation feedback loop and an active rectifier with maximum efficiency tracking technique. The feedback loop enables the control of the power delivered to the load by means of a frequency modulation of the receiver load, introducing an efficiency loss of only 1.64 %. The active rectifier maximizes the efficiency of the link through a second feedback calibration loop of the off-transition of the active diodes, showing a Voltage Conversion Ratio of 0.98 and a Power Conversion Efficiency between 0.86 and 0.91 for a wide range of load conditions. The chip was designed in the 180 nm BCD-on-SOI XFAB technology and evaluated with accurate electrical simulations and Monte Carlo runs
Pixel Design Driven Performance Improvement in 4T CMOS Image Sensors: Dark Current Reduction and Full-Well Enhancement
No full textDark current (DC) limits the optical performance of CMOS image sensors. The main sources of the DC in a modern submicrometer process are the defects induced by the shallow trench isolation fabrication process steps. In this brief, we present a pixel layout technique to reduce the impact of these defects by removing the trench-oxide between the two adjacent edges of neighboring photodiodes (PDs). This isolation scheme relies only on the p-well layer and provides the further advantage of requiring less area. Hence, a larger PD can be designed, leading to an increased pixel fill factor. Experimental results show that this approach reduces the DC by 21% and increases the linear full well capacity by approximately 9%
Mixed device-circuit simulations of 6T/8T SRAM cells employing tunnel-FETs
No full textThe scaling of the supply voltage VDD is an effective way to reduce power
dissipation in digital circuits. The ION/IOFF ratio in conventional MOSFETs is limited by the
thermionic electron emission, corresponding to a minimum sub-threshold swing SSmin ~ 60
mV/dec. Novel device architectures based on different operating principles are therefore
gaining interest in order to reduce the static power dissipation (lowering IOFF at the same VDD)
or the dynamic power (reducing VDD for the same IOFF) without affecting the performance
( ION). In the tunnel-FETs (TFETs), the conduction mechanism is the band-to-band tunneling
(Fig.1), enabling a sub-60 mV/dec region (Fig.2) as demonstrated by experiments [1]. Among
the main issues that may limit the employment of TFETs in digital circuits, we recall the drain
current (ID) unidirectionality and the low ION
Performance analysis of different SRAM cell topologies employing tunnel-FETs
No full textTunnel-FET is one of the most promising candidates to replace CMOS in low-power (LP) applications [1], featuring a sub-threshold slope (SS) below the 60mV/dec limit of MOSFET. However, the intrinsic asymmetry of TFETs, makes them good transistors only for a current flowing from drain to source and prevents their use as access transistors (AT) in the 6T SRAM cell. In this paper, we use TCAD mixed device-circuit simulations [2] of symmetric 6T SRAM cells, implemented with the n-type SiGe/Si TFET and p-type strained-Si TFET designed in [3] (Fig. 1) for VDD as low as 0.2V. The gate metal work-functions were set to match the off-current for LP applications (10pA/μm). For comparison purposes, both N- and P-MOS were also designed with the same double-gate SOI structure. The ID-VGS curves of the TFETs (Fig.2) show that the sub-60mV/decade region is confined to ultra low voltage regime (below 0.25 V) and that ambipolarity is very limited in these devices. ID(VDS) in Fig.3 show the lower output conductance of the TFETs w.r.t. to MOS. © 2014 IEEE
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