1,721,488 research outputs found
Proceedings of the conference on Design, Automation and Test in Europe
No full textProceedings of the conference on Design, automation and test in Europe - DATE 200
Constant testability of combinational cellular tree structures
No full textThis paper presents various approaches for testing cellular tree structures with a constant number of test vectors, that is, independent of the number of cells (size of the tree). The necessary and sufficient conditions which must be satisfied in the state table of a basic combinational cell for achieving C-testability and one-step C-testability in a homogeneous tree, are proved. The design modifications required to accomplish this objective in arbitrary cells, are discussed. It is proved that three additional rows and three additional columns are needed in the state table of a cell; the characteristics of the additional states are also analyzed. The complexity of the proposed testing process is quadratic with respect to the number of entries in the state table of a cell. Illustrative examples are also give
Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems - Embedded Systems Week 2009 CODES+ISSS’09 • CASES’09 • EMSOFT’09
No full textA hierarchical test generation approach for large controllers
No full textA testing approach targeted at Hardware Description Language (HDL)-based specifications of complex control devices is proposed. For such architectures, gate-level test pattern generators require insertion of scan paths to enable the flat gate-level representations to be efficiently handled. In contrast, we present a testing methodology based on the hierarchical finite state machine model. Our approach allows the generation of compact test sets with very high stuck-at fault coverages, without any design-for-testability logic other than hardware reset. This method can be used any time the functional information is available together with the gate-level structural description. High fault coverages are achieved with smaller test lengths and execution times with respect to state-of-the-art gate-level test pattern generator
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