1,721,135 research outputs found
Spiker: an FPGA-optimized Hardware acceleration for Spiking Neural Networks
Full text linkSpiking Neural Networks (SNN) are an emerging type of biologically plausible
and efficient Artificial Neural Network (ANN). This work presents the
development of a hardware accelerator for a SNN for high-performance inference,
targeting a Xilinx Artix-7 Field Programmable Gate Array (FPGA). The model used
inside the neuron is the Leaky Integrate and Fire (LIF). The execution is
clock-driven, meaning that the internal state of the neuron is updated at every
clock cycle, even in absence of spikes. The inference capabilities of the
accelerator are evaluated using the MINST dataset. The training is performed
offline on a full precision model. The results show a good improvement in
performance if compared with the state-of-the-art accelerators, requiring
215{\mu}s per image. The energy consumption is slightly higher than the most
optimized design, with an average value of 13mJ per image. The test design
consists of a single layer of four-hundred neurons and uses around 40% of the
available resources on the FPGA. This makes it suitable for a time-constrained
application at the edge, leaving space for other acceleration tasks on the
FPGA.Comment: 6 pages, 3 figures, 4 table
Real-time Embedded System Fault Injector Framework for Micro-architectural State Based Reliability Assessment
Full text linkThe increasing complexity of Safety-Critical Real-Time Embedded Systems (SACRES) presents significant challenges regarding reliability, security, and trustworthiness. Key concerns include the system’s vulnerability to instantaneous voltage spikes, electromagnetic interference, neutron strikes, and temperatures out of range, which can induce bit-flipping and consequentially temporary corruption of stored memory data and soft errors. These errors may result in system faults that could push the system into dangerous states. In high-stakes fields like automotive, aerospace, and avionics, such failures can have serious, real-world consequences, potentially endangering lives. This paper introduces an innovative, fully configurable fault injection tool designed to monitor and analyze the micro-architectural state of the system. This tool allows a tailored injection campaign, including both CPU registers and RAM, with a flexible fault model able to inject single and multi-bit-flipping in the application and Operating System (OS) space. Tracking the architectural events using the microprocessor’s Performance Monitoring Unit (PMU) and debugging interface. A key feature is its ability to ensure the repeatability of fault injections, which focus on bit-flipping in memory systems. The results of these fault injections allow for a detailed analysis of how soft errors affect system performance, output integrity, and timing predictability, all of which are critical in SACRES
Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge
Full text linkIncluding Artificial Neural Networks in embedded systems at the edge allows applications to exploit Artificial Intelligence capabilities directly within devices operating at the network periphery. This paper introduces Spiker+, a comprehensive framework for generating efficient, low-power, and low-area customized Spiking Neural Networks (SNN) accelerators on FPGA for inference at the edge. Spiker+ presents a configurable multi-layer hardware SNN, a library of highly efficient neuron architectures, and a design framework, enabling the development of complex neural network accelerators with few lines of Python code. Spiker+ is tested on two benchmark datasets, the MNIST and the Spiking Heidelberg Digits (SHD). On the MNIST, it demonstrates competitive performance compared to state-of-the-art SNN accelerators. It outperforms them in terms of resource allocation, with a requirement of 7,612 logic cells and 18 Block RAMs (BRAMs), which makes it fit in very small FPGA, and power consumption, draining only 180mW for a complete inference on an input image. The latency is comparable to the ones observed in the state-of-the-art, with 780us/img. To the authors\u27 knowledge, Spiker+ is the first SNN accelerator tested on the SHD. In this case, the accelerator requires 18,268 logic cells and 51 BRAM, with an overall power consumption of 430mW and a latency of 54 us for a complete inference on input data. This underscores the significance of Spiker+ in the hardware-accelerated SNN landscape, making it an excellent solution to deploy configurable and tunable SNN architectures in resource and power-constrained edge applications
Artificial Resilience in neuromorphic systems
Full text linkBiological beings are intrinsically resilient. This means that they are able to continue to perform a task even if they are partially damaged or if some parts of them don’t work as expected. This is true also for the human brain. The research in these last years, however, has been concentrated on Artificial Intelligence (AI), to try to emulate the capabilities of the brain to improve itself, learn- ing from experience. Artificial Resilience (AR) is something not explored in detail yet. This four pages abstract present a Ph.D. path dedicated to the extensive study of Artificial Resilience in all its aspects. The study will target neuromorphic systems, in particu- lar Spiking Neural Networks, an emerging type of neural network models that try to mimic the behavior of a biological brain in a faithful way. In addition to this they are in general more suitable for an hardware acceleration. The goal of the Ph.D. is to realize a com- plete neuromorphic accelerator, configurable and resilient, and to apply it to improve the resilience of other electronic systems. Such an accelerator will be able to target area- and power-constrained applications in mission-critical environments, providing a more efficient alternative to classical techniques like Error Correction Codes (ECC) or redundancy to improve the robustness of a complex electronic system
Design Space Exploration of Approximate Computing Techniques with a Reinforcement Learning Approach
Full text linkApproximate Computing (AxC) techniques have become increasingly popular in trading off accuracy for performance gains in various applications. Selecting the best AxC techniques for a given application is challenging. Among proposed approaches for exploring the design space, Machine Learning approaches such as Reinforcement Learning (RL) show promising results. In this paper, we proposed an RL-based multi-objective Design Space Exploration strategy to find the approximate versions of the application that balance accuracy degradation and power and computation time reduction. Our experimental results show a good trade-off between accuracy degradation and decreased power and computation time for some benchmarks
Optimization of synthetic oscillatory biological networks through Reinforcement Learning
Full text linkIn the expanding realm of computational biology, Reinforcement Learning (RL) emerges as a novel and promising approach, especially for designing and optimizing complex synthetic biological circuits. This study explores the application of RL in controlling Hopf bifurcations within ODE-based systems, particularly under the influence of molecular noise. Through two case studies, we demonstrate RL’s capabilities in navigating biological systems’ inherent non-linearity and high dimensionality. Our findings reveal that RL effectively identifies the onset of Hopf bifurcations and preserves biological plausibility within the optimized networks. However, challenges were encountered in achieving persistent oscillations and matching traditional algorithms’ computational speed. Despite these limitations, the study highlights RL’s significant potential as an instrumental tool in computational biology, offering a novel perspective for exploring and optimizing oscillatory dynamics within complex biological systems. Our research establishes RL as a promising strategy for manipulating and designing intricate behaviors in biological networks
CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN Bus
Full text linkThe Controller Area Network (CAN) protocol, essential for automotive embedded systems, lacks inherent security features, making it vulnerable to cyber threats, especially with the rise of autonomous vehicles. Traditional security measures offer limited protection, such as payload encryption and message authentication. This paper presents a novel Intrusion Detection System (IDS) designed for the CAN environment, utilizing Hardware Performance Counters (HPCs) to detect anomalies indicative of cyber attacks. A RISC-V-based CAN receiver is simulated using the gem5 simulator, processing CAN frame payloads with AES-128 encryption as FreeRTOS tasks, which trigger distinct HPC responses. Key HPC features are optimized through data extraction and correlation analysis to enhance classification efficiency. Results indicate that this approach could significantly improve CAN security and address emerging challenges in automotive cybersecurity
GRAIGH: Gene Regulation accessibility integrating GeneHancer database
Full text linkSingle-cell assays for transposase-accessible chromatin sequencing data represent a potent tool for exploring the epigenetic heterogeneity within cell populations. Despite their power, understanding the chromatin accessibility landscape poses challenges. This study introduces Gene Regulation Accessibility Integrating GeneHancer (GRAIGH), a novel approach to interpreting genome accessibility by integrating information from the GeneHancer database, detailing genome-wide enhancer-to-gene associations. Initially, we outline the methods for integrating GeneHancer with scATAC-seq data. This involves creating a new matrix where GeneHancer element IDs replace traditional accessibility peaks as features. Subsequently, the paper assesses the method’s ability to analyze data and detect cellular heterogeneity. Notably, our findings demonstrate the selective accessibility of GeneHancer elements for distinct cell types, with connected genes serving as precise marker genes. Furthermore, we explore the specificity of GeneHancer element accessibility, highlighting their high selectivity against gene activity. This investigation underscores the potential of Gene Regulation Accessibility Integrating GeneHancer in unraveling the complexities of chromatin accessibility, offering insights into the nuanced relationship between accessibility and cellular heterogeneity
Assessing LLMs models’ knowledge of automotive cyberthreats benchmarking autoISAC framework
Full text linkLarge Language Models (LLMs) are gaining traction in cybersecurity applications, offering both promising opportunities and potential new risks. The use of these models in sub-domains such as automotive is still in its early stages. In this work-in-progress study, we use GPT-4o from OpenAI to generate a preliminary set of domain-relevant cybersecurity questions exploiting the Automotive Information Sharing and Analysis Center (Auto-ISAC) framework, which we then refined through manual validation. We exploited the final set of 25 questions to evaluate the performance of five LLMs models. Then, these questions were administered through a survey to a group of 17 domain experts, allowing us to compare this baseline with the results from the LLMs. From our preliminary findings, we found that LLMs reached a mean of 91.2% of correct answers on the test while human experts’ performance reached 64.7%. This study lays the groundwork for future investigations into the use of LLMs in the automotive-security domain and into the safe and trustworthy exploitation of LLMs
Prediction of the Impact of Approximate Computing on Spiking Neural Networks via Interval Arithmetic
Full text linkApproximate Computing (AxC) techniques allow trade-off accuracy for performance, energy, and area reduction gains. One of the applications suitable for using AxC techniques are the Spiking Neural Networks (SNNs). SNNs are the new frontier for artificial intelligence since they allow for a more reliable hardware design. Unfortunately, this design requires some area minimization strategies when the target hardware reaches the edge of computing. In this work, we first extract the computation flow of an SNN, then employ Interval Arithmetic (IA) to model the propagation of the approximation error. This enables a quick evaluation of the impact of approximation. Experimental results confirm the model’s adherence and the capability of reducing the exploration time
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