1,721,145 research outputs found
Oscillatore LC
No full textll brevetto riguarda un nuovo array di oscillatori LC accoppiati.
La novità risiede nella modalità utilizzata per accoppiare le varie celle. Nella topologia classica si utilizza in ogni cella un transconduttore per bilanciare le perdite del tank e uno per accoppiare l'oscillatore al resto della rete. Nella presente soluzione invece, è presente un solo transconduttore per cella, che contemporaneamente bilancia le perdite e concede l'accoppiamento.
Il principale vantaggio della soluzione proposta è la riduzione della up-conversion del rumore flicker in rumore di fase 1/f^3, effetto molto limitante nelle realizzazioni CMOS
Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling
No full textThis paper investigates nature and effects of jitter on
the clock edge that triggers the sample/hold used in direct-sampling and IF-sampling receiver architectures. The impact of
the aperture uncertainty is theoretically discussed, simulated,
and measured in the case of the high-frequency front-end of a 16-bit 65 MS/s analog–digital converter. Both characterizations of the phenomenon are considered: in the frequency domain [single-sideband to carrier ratio (SSCR), or phase noise] and in the time domain (aperture jitter)
Sampling device having an intrinsic filter
No full textA sampling device for sampling an input signal having intrinsic filter properties. The sampling device samples a continuous analog input signal according to a sampling signal. The sampling device includes a first sampling switch for sampling the input signal, in response to a sampling signal, to create a first set of samples. Furthermore, the sampling device incorporates a time delay device for time delaying the first set of samples. The sampling device also includes a phase shift device for phase shifting the input signal. The phase delayed input signal is then fed into a second sampling switch for sampling in response to the sampling signal to create a second set of samples. Further, a summer is incorporated to sum the first set of samples with the second set of samples to create the output samples
A time-digital converter and an electronic system implementing the converter
No full textA time-digital converter (100) comprising: an adjustable delay device (D1; DN) for generating a delayed signal (S1) provided with a delay adjusting input (5), and an arbiter device (FF1) for receiving the delayed signal and a reference signal (So) on corresponding inputs and for supplying an output signal (SD1) to an output (O1) indicative of a relative timing of the signals at its inputs. The converter further comprises: a calibration delay device (Dbm) for supplying the reference signal to the arbiter device, and a calibration filter (F1) connectable to said output (O1) for providing input (5) of the adjustable delay device with a delay adjusting signal (S21) depending on the output signal of the arbiter device
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs
Full text linkDigital fractional-N phase-locked loops (PLLs) are an attractive alternative to analog PLLs in the design of frequency synthesizers for wireless applications. However, the main obstacle to their full acceptance in the wireless-systems arena is their higher content of output spurious tones, whose level is ultimately set by the nonlinearity of the time-to-digital converter (TDC). The known methods to improve the linearity of the TDC either increase its dissipation and phase noise or require slow foreground calibrations. By contrast, the class of digital PLLs based on a one-bit TDC driven by a multi-bit digital-to-time converter (DTC) substantially reduces power dissipation and eliminates the TDC nonlinearity issues. Although its spur performance depends on DTC linearity, the modified architecture enables the application of a background adaptive pre-distortion which does not compromise the PLL phase-noise level and power consumption and is much faster than other calibration techniques. This paper presents a 3.6-GHz digital PLL in 65-nm CMOS, with in-band fractional spurs dropping from -39 to -52 dBc when the pre-distortion is enabled, in-band phase noise of -103 dBc/Hz and power con- sumption of 4.2 mW
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