91 research outputs found
Influence of substrate off-cut on the defect structure in relaxed graded Si-Ge/Si layers
Relaxed graded Si-Ge/Si layers can be used in a variety of micro-electronics applications such as templates for III-V/Si integration, in high speed field effect transistor (FET) structures and as detectors in optical communication Each of these applications requires a different final Ge concentration in the graded Si-Ge layer. With increasing Ge content in the graded layer, some of the materials concerns that need to be addressed are- (i) a high surface roughness, (ii) the formation of dislocation pile-ups, and (iii) an increase in the threading dislocation density. We have shown that there is a substantial improvement in the surface roughness and the dislocation pile-up density of the graded Si-Ge layers by depositing on (001) 6 degrees off-cut substrates. The substrate miscut also facilitates favorable intersections of {111} planes that aid reactions between the 60 degrees dislocations to form edge dislocations with Burgers vectors of the type 1/2 and resulting in a novel hexagonal dislocation structure. Such reactions occurred more readily in the Ge-rich regions of the graded layers where the growth temperature was high enough to aid dislocation climb. The edge dislocations with in-plane Burgers vectors lack a tilt component and the decreased rate of tilting in the Ge-rich regions is confirmed by triple crystal X-ray reciprocal space maps. This novel dislocation structure offers opportunities to explore new processes which may eliminate spatially variant strain fields in relaxed epitaxial layers
Effect of Mo doping on accelerated growth of C-54 TiSi2: Evidence for template mechanism
Effect of Mo Doping on Formation of Ti-Silicide Phases Studied by HRTEM
AbstractThe phase sequence of the RTP induced reaction at T=650°C has been studied. We found that pre-amorphization of poly-Si substrates does not change the reaction path. i.e. Ti5Si4, and C-49 TiSi2 phases were formed_ with the latter growing upon further anneal. In the Mo doped poly-Si/Ti system the C-54 TiSi2 phase has formed along with Ti5Si4 and two Mo silicide phases, MoSi2 and Mo5Si3; no C-49 TiSi2 was observed. We show that the reaction in the Mo doped system follows the template mechanism with MoSi2 and Mo5Si3 based phase acting as template phases for accelerated growth of C-54 TiSi2.</jats:p
Mechanism of low temperature C54 TiSi2 formation bypassing C49 TiSi2: Effect of Si microstructure and Mo impurities on the Ti–Si reaction path
Depletion isolation effect in Vertical MOSFETS during transition from partial to fully depleted operation
A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm. For pillar thicknesses between 200–60 nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias Vdc for which the increased drain–current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60–10 nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate–gate coupling contribute to the drain–current for pillar thicknesses between 100–40 nm
Depletion-Isolation Effect in Vertical MOSFETs During the Transition From Partial to Fully Depleted Operation
A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10 nm. For pillar thicknesses between 200–60 nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias Vdc for which the increased drain–current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60–10 nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate–gate coupling contribute to the drain–current for pillar thicknesses between 100–40 nm
Low Temperature Formation of C54 TiSi<sub>2</sub> Bypassing the C49 Phase: Effect of Si Crystallinity, Metallic Impurities and Applications TO 0.10 μm CMOS
ABSTRACTThe mechanism and evolution from the early stages of the Ti/Si reaction by rapid thermal processing (RTP) at 650°C in the presence of Mo doping was studied and compared to the case without Mo doping; for amorphous, polycrystalline and single crystal (100) Si substrates. It was found that for Mo doped polycrystalline Si or Mo doped amorphous Si, the low resitivity C54 TiSi2 phase nucleates at the Ti/Si interface and grows following diffusion limited kinetics, bypassing the nucleation of the high resistivity C49 TiSi2 phase. The conventional phase sequence, with C49 TiSi 2 nucleation and growth, was observed on Mo doped (100) Si and all samples without Mo. The mechanism of early C54 nucleation was identified by high resolution transmission electron microscopy (HRTEM): at early stages of the reaction, precursor silicide phases lattice matched to C54 TiSi2 nucleate at the Ti/Mo doped Si interface, and act as templates for epitaxial nucleation of C54 TiSi2. Two such phases were observed, MoSi2 and a phase with spacings of 2.26 Å and 4.2 Å. Image simulations suggest that the structure of the second template phase is based on Mo5Si3. Similar kinetics were observed on large structures and narrow lines for Mo doped Si (except for the case of (100) Si), indicating that this growth mechanism eliminates the linewidth dependence. Implementation on a 0.10 μm CMOS technology of a process combining Mo doping with pre-amorphization (PAI) achieves low source/drain (S/D) sheet resistance, and the first Ti salicide process with low gate sheet resistance down to 0.06 μm.</jats:p
Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
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