196,052 research outputs found
Instability of Dynamic- RONand Threshold Voltage in GaN-on-GaN Vertical Field-Effect Transistors
No full textThis paper investigates the recoverable degradation of GaN-on-GaN vertical transistors under positive gate bias stress. Based on combined pulsed measurements and constant voltage stress test, we demonstrate the following original results: 1) when subjected to moderate gate stress (0 V <; V GS <; 3 V), the devices show a negative threshold voltage shift, which is correlated with a decrease in on-resistance. This process is ascribed to the detrapping of electrons from the Al 2 O 3 insulator, induced by a low positive bias and 2) for high stress bias(V GS ≥ 5 V), a strong positive shift in threshold voltage is observed. This effect, which shows a slow recovery, is ascribed to the injection of electrons from the accumulation region (channel) toward the dielectric. Temperature-dependent measurements and 2-D simulations were carried out to support the hypothesis on degradation, and to evaluate the contribution of surface and bulk current in the n-GaN drift layer
Positive and negative threshold voltage instabilities in GaN-based transistors
No full textThis paper reviews the main mechanisms responsible for bias-temperature instability (BTI) in GaN-based high electron mobility transistors. In the first part of the article, we focus on the threshold voltage instabilities of GaN-based MIS-HEMTs submitted to positive and negative gate bias. We demonstrate that the shift in threshold voltage originates from the trapping/de-trapping of defects located at the insulator/semiconductor interface and/or in the bulk dielectric. In the second part of the paper, we describe the threshold voltage instabilities of GaN-transistors with p-GaN gate, designed specifically for normally-off operation. We present original data indicating that under positive gate bias these devices with p-GaN gate may show a negative threshold voltage shift, which is fully recoverable. This effect is ascribed to the injection of holes under the gate contact, and to the corresponding accumulation of positive charge, possibly at the p-GaN/AlGaN interface.
The results described within this paper provide an up-to-date description of the most relevant trapping processes that impact on the stability of threshold voltage and on-resistance in GaN-based transistors
Reliability of power devices: Bias-induced threshold voltage instability and dielectric breakdown in GaN MIS-HEMTs
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Characterization of charge trapping mechanisms in GaN vertical Fin FETs under positive gate bias
No full textIn this paper, we present a comprehensive analysis of the charge trapping mechanisms that affect the GaN based vertical Fin FETs when the devices are submitted to positive gate bias. Devices with higher channel width show lower threshold voltage: with 2D simulations of the electron density we are able to explain the phenomenon and propose a trade-off to improve the technology. By using double pulse measurements and threshold voltage transients, two trapping/detrapping mechanisms under positive gate bias can be identified according to two voltage ranges. At low positive gate bias, electrons (previously trapped inside the oxide during the fabrication process) are detrapped towards the gate metal (mechanism 1). At higher gate bias, electrons are trapped at the GaN/oxide interface, moving the threshold towards positive values (mechanism 2). The second mechanism is observable at higher time of stress and it is predominant for higher voltages. Moreover, mechanism 2 is found to be recoverable only when the device is exposed to UV-light and electrons trapped in a specific level in the oxide acquire the energy necessary to escape and reach the n-type GaN and/or the UV-generated holes accumulate at the interface may reduce the trapped electron density. We demonstrate our hypothesis by calculating the interface state density in trapping/detrapping conditions by using photo-assisted Capacitance-Voltage measurements
Dr. Duane M. Jackson, Morehouse College, July 2011
No full textThis video is a conversation with Dr. Duane M. Jackson. Dr. Jackson talks about his paper, "Recall and the Serial Position Effect: The Role of Primacy and Recency on Accounting Students' Performance." Jackie Daniel, AUC Woodruff Library, is the interviewer
NUV-HD SiPMs with Metal-filled Trenches
No full textIn this contribution we would like to present a breakthrough improvement of the optical crosstalk between SPADs in SiPMs. In the framework of a collaboration between FBK and Broadcom we developed narrow metal-filled trenches that greatly suppress the optical crosstalk while maintaining a high fill factor and, in turn, photon detection efficiency. In particular, the new metal in trench detector (NUV-HD-MT) features an internal crosstalk almost 10 times lower than previous NUV-HD FBK SiPMs and can operate up to 17 V of excess bias voltages without any divergence of the correlated noise. The higher operating bias compensates the small loss in fill factor due to the insertion of the metal layer in the trenches and allows the NUV-HD-MT to reach PDE in excess of 60% with 40 μm cells. Together with a SiPM layout optimized for timing, the extended bias range allows to operate the detector with higher gain and low level of correlated noise, improving the CTR performance below 90 ps using 4x4 mm2 detectors coupled to 3x3x5 mm3 LYSO:Ce crystals and readout by a conventional front-end. The characteristics described above allow this detector to be considered as a good candidate for the upgrade of ToF-PET machines
"Reflections on the subject of Emigration from Europe with a view to Settlement in the United States" By M. Carey.
No full text"Reflections on the subject of Emigration from Europe with a view to Settlement in the United States: containing bried sketches of the moral and political character of those states.
By M. Carey, member of the American philosophical, and of the American Antiquarian Society, and author of The Olive Branch, Cindiciae Hibernicae, essays on banking, on political economy, and on internal improvement.
To which are now added the English editor's comments on the subject; together with Important Advice to Emigrants, and Cautions Against Impositions Practiced in the Outports
Degradation Mechanisms of GaN HEMTs with p-Type Gate under Forward Gate Bias Overstress
No full textThis paper investigates the degradation of GaN-based HEMTs with p-type gate submitted to positive gate bias stress. Based on combined electrical and optical testing, we demonstrate the existence of different degradation processes, depending on the applied stress voltage VGstress: 1) for VGstress< 7 V, no significant degradation is observed, thus demonstrating a good stability of the analyzed technology; 2) for 7 V< VGstress < 11.5 V, a negative shift in threshold voltage (Vth) is observed, well correlated with a decrease in the gate leakage current and of the luminescence signal associated with hole injection. The negative Vth shift is ascribed to the trapping of holes in the AlGaN and/or p-GaN/AlGaN interface; and 3) for VGstress 12 V, threshold voltage recovers its initial value. This is ascribed to a net-negative charge, generated either by the trapping of electrons injected from the 2-D electron gas to the AlGaN or to the de-trapping of the holes injected in 2). The results described within this paper provide relevant information for understanding the degradation dynamics of normally off GaN transistors submitted to extremely high gate voltage levels far beyond maximum use
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