1,721,184 research outputs found
Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers
Get PDFIn wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient
Look-ahead sigma-delta modulation and its application to super audio CD
Get PDFIn this thesis the possibilities of look-ahead sigma-delta modulation are investigated, with the objective to improve the signal conversion quality compared to that of a normal SDM. This investigation is first made for look-ahead sigma-delta modulation in general, while from chapter 6 onwards the focus is on general purpose 1-bit DD conversion. In chapter 10 a look-ahead realization that is specifically optimized for Super Audio CD usage is presented. In chapter 2, the basics of traditional sigma-delta modulation are reviewed, and a number of SDM performance indicators are introduced.These indicators can be divided in two classes, i.e. indicators that are of a general nature and that are applicable to all data converter types, and indicators that are specific for Sigma-Delta Modulators. In chapter 3, an investigation is made of the potential difference between the SINAD performance of a (non-linear) 1-bit SDM for a steady-statesignal and that of a non-steady-state signal. For this purpose a time-domain SINAD measurement method is introduced that allows for SINAD performance characterization of non-steady-state signals. The outcome of this investigation is that there is no significant difference between the performance of non-steady-state and steady-state signals, and that the classical frequency domain SINAD measurement succes. An abstract model of a noise-shaping quantizer is derived in chapter 4. This model introduces the concept of a cost function, which is an indication of the quality of a signal or an encoding solution. In the case of a normal SDM, the output of the loop filter can be considered as a cost value. The negative feed-back strategy attempts to minimize the absolute value of this cost, but can not guarantee this result because of the loop delay. In chapter 5, the noise-shaping quantizer model is modified to support look-ahead, and the main look-ahead principle is explained. Instead of relying on a feed-back strategy that attempts to minimize the instantaneous cost value, i.e. a local optimization strategy that does not attempt to find the solution that is optimal in a global sense, the impact of the selected output symbol on the future cost values is taken into account by a quantizer with look-ahead. Although only with an infinite amount of look-ahead the global optimal encoding solution can be found, it is concluded that already with a limited amount of look-ahead an improvement in the signal conversion performance can be obtained. The main disadvantage of incorporating look-ahead into an SDM is the increase of the resource costs. The benefits, primarily an increase of the stability and a reduction of the distortion, are the biggest in the case of a 1-bit converter, since here the quantizer is severely non-linear. Up till now, the analysis was performed for look-ahead Sigma-Delta converters in general. The possibilities for realizing a look-ahead enabled Sigma-Delta ADC are investigated, but because of the large number of identical loop filters that are required, the idea of an ADC with look-ahead is rejected. The potential for a DD converter with look-ahead is large, but also here the computational cost should be reduced compared to the straight-forward full look-ahead solution. From this point onwards, the work focusses on 1-bit look-ahead DD sigma-delta modulation, although most of the results can be directly applied to multi-bit look-ahead sigma-delta modulation. The possibilities for reducing the computational cost of a look-ahead DD converter are explored in chapter 6. Two possibilities are identified, i.e. an optimization of the full look-ahead algorithm, and a reduction of the solution space. It is found that the possibilities for optimizing the full look-ahead algorithm are limited, and that the full look-ahead approach can only by used for look-ahead depths up to 16-20 samples. The reduction of the solution space, a process called pruning, offers good possibilities for the realization of a large look-ahead depth at a limited computational cost. Several ideas for realizing pruned look-ahead modulators are presented, that are explored in detail in the next chapters. Chapter 7 presents a full analysis of the Trellis sigma-delta modulation algorithm. This algorithm is the first pruned look-ahead sigma-delta modulation algorithm found in literature. It is a derivative of the full look-ahead algorithm and uses concepts from Trellis (Viterbi) decoding, hence the name. In the Trellis sigma-delta modulation algorithm, at all times, a total number of 2N potential solutions (paths) are investigated, of which the most recent N symbols are different for all the solutions. The output symbol of the converter is found by tracing back any of the 2N paths L time steps. This approach results in a converter that has an improved linearity and better stability than a normal SDM, although the computational load is very high. In chapter 8, an effcient derivative of the Trellis SDM, called the Efficient Trellis SDM, is introduced. Instead of exploring 2N solutions in parallel, only M solutions out of the possible 2N are tracked. This is possible since only a fraction of all the 2N solutions contributes to the final output. The selection of which paths to keep is based on the accumulated path cost, i.e. paths with a low cost have a large probability to be part of the output and are selected, whereas more expensive paths are rejected. Compared to the Trellis sigma-delta modulation algorithm, the computational load is reduced by several orders of magnitude, while at the same time improvements in the linearity and stability are obtained. A final reduction of the computational load is achieved in chapter 9, where the Pruned Tree sigma-delta modulation algorithm is presented. This algorithm is a practical realization of the pruned look-ahead approach as derived in chapter 6. A total of M paths are tracked, with no constraints on the solution space coverage imposed. The result of this approach is that a performance level that is slightly better than that of the Efficient Trellis sigma-delta modulation algorithm is realized, at a significantly reduced computational load. In chapter 10, the Pruned Tree sigma-delta modulation algorithm for SA-CD is presented. The algorithm has a better compatibility with Super Audio CD, because it generates bitstreams that result in a high lossless data compression gain. This is achieved by adding a cost function to the look-ahead filter that measures the predictability of the output signal. This addition results in an output bitstream that is of a high signal quality, but that is also very predictable, such that the amount of required disc storage space after lossless data compression reduces. This reduction of the required storage space is of great importance, since it solves potential playback duration issues. The addition of the prediction cost function has only a minimal impact on the SNR, while the distortion and the noise-modulation performance of the converter are strongly reduced, resulting in the ideal Sigma-Delta converter for high-end audio applications. All of the previously discussed look-ahead techniques are compared in chapter 11. The outcome of this comparison is that the normal Pruned Tree sigma-delta modulation algorithm is the best choice if the converter is not intended for audio applications, since it offers the highest SNR, very good linearity, and the largest stability at the minimal computational cost. In the case of a high-end application for Super Audio CD, the Pruned Tree sigma-delta modulation algorithm for SA-CD is the best choice because of the constant in-band noise-floor and the higher compression gains that are obtained on the output bitstream. In chapter 12, an investigation is made of the apparent limit on the obtainable SNR of a 1-bit look-ahead SDM. The outcome of this investigation is that there is a point of maximal noise shaping, which depends on the filter order. At the point of maximal noise shaping the system is critically stable, and increasing the corner frequency of the loop filter above this point will not change the noise-shaping characteristics, i.e. the look-ahead system forces the same noise shaping as obtained for the critically stable point. If, instead of increasing the loop-filter corner frequency further, a higher filter order is selected in combination with a lower loop-filter corner frequency, a more aggressive noise shaping can be realized that results in a higher SNR. Since the more aggressive noise shaping causes a reduction of the stability of the SDM, more parallel paths are required to stabilize the system. Although with this approach a world-record SNR for a 1-bit noise-shaped signal has been achieved, it is still far away from the limits imposed by information theory. As such, in practice the SNR is only limited by the amount of available computational power that is required to stabilize the higher order filters. Finally, in chapter 13 the general conclusions on the work described in this thesis are presented
Characterization and application of a mismatch detector for adaptive antenna impedance matching
Get PDF
- …
