304 research outputs found
Special Session: STT-MRAMs: Technology, Design and Test
No full textSTT-MRAM has long been a promising non-volatile memory solution for the embedded application space owing to its attractive characteristics such as non-volatility, low leakage, high endurance, and scalability. However, the operating requirements for high-performance computing (HPC) and low power (LP) applications involve different challenges. This paper addresses different aspects of STT-MRAM; it will cover state-of-the-art, some new results and future challenges related to technology, design and test. While STT-MRAM devices have shown encouraging performance metrics at device-level, a key challenge has been achieving backend-of-line (BEOL) CMOS compatibility, while retaining the benefits of low power operation. Scaling demands to improve data densities have placed additional challenges in terms of addressing the impact of process-induced damage on device performance at CD < 100 nm. In addition, the paper discusses the design of reliable read mechanism considering the variability effects. Moreover, the failure of traditional fault modeling and test approaches in model STT-MRAM unique defects for appropriate test solutions is demonstrated in this paper based on silicon data. Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
Testing of Interconnect and Contact Defects in STT-MRAMs
No full textSpin-transfer-torque magnetic random access memory (STT-MRAM) is regarded as one of the most promising non-volatile memory (NVM) technologies, which has the potential to replace the traditional memories in the modern memory hierarchy. Due to some advantages such as non-volatility, fast access speed, low leakage power and high density, more and more research attention is being paid to STT-MRAM. To enable the mass production of STT-MRAM, high-quality and cost-efficient test solutions are the prerequisites. In this thesis, the comprehensive investigation for testing interconnect and contact defects in STT-MRAMs will be presented. The complete defect space for interconnect and contact defects in STT-MRAMs is systematically defined, which are modelled as linear resistors. All theoretically possible faults are defined in a fault space, followed by a methodology to validate these faults under inter-cell magnetic coupling in the presence of defined defects. In this way, accurate fault modelling is performed to guarantee the occurrence of realistic faults in STT-MRAMs. We observed the specific STT-MRAM fault model—passive neighborhood pattern sensitive fault (PNPSF). Based on the fault validation results, an effective march test algorithm(7N) is proposed for interconnect and contact defects in STT-MRAMs.Electrical Engineering | Microelectronic
Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions
No full textAs STT-MRAM mass production and deployment in industry is around the corner, high-quality yet cost-efficient manufacturing test solutions are crucial to ensure the required quality of products being shipped to end customers. This dissertation focuses on STT-MRAM testing, covering three abstraction levels: manufacturing defects, fault models, and test solutions. We apply the advanced device-aware test (DAT) approach to STT-MRAM defects, including resistive defects on interconnects and STT-MRAM device-internal defects such as pinhole defects, synthetic anti-ferromagnet flip defects, intermediate state defects. With the derived accurate defect models calibrated by silicon data, a comprehensive fault analysis based on SPICE circuit simulations is performed. STT-MRAM unique faults are identified, including both permanent faults and intermittent faults. Based on the obtain fault models, high-quality test solutions are proposed. Additionally, this dissertation also explores the impact of magnetic coupling and density on STT-MRAM performance for robust designs.Computer Engineerin
Defect and Fault Modeling Framework for STT-MRAM Testing
No full textSTT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This article presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate fault models which reflect the physical defects appropriately, and thereafter optimal and high-quality test solutions. An overview and classification of manufacturing defects in STT-MRAMs are provided with an emphasis on those related to the fabrication of magnetic tunnel junction (MTJ) devices, i.e., the data-storing elements. Defects in MTJ devices need to be modeled by adjusting the affected technology parameters and subsequent electrical parameters to fully capture the defect impact on both the device's electrical and magnetic properties, whereas defects in interconnects can be modeled as linear resistors. In addition, a complete single-cell fault space and nomenclature are defined, and a systematic fault analysis methodology is proposed. To demonstrate the use of the proposed framework, resistive defects in interconnect and pinhole defects in MTJ devices are analyzed for a single 1T-1MTJ memory cell. Test solutions for detecting these defects are also discussed.Computer EngineeringQuantum & Computer Engineerin
CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out
No full textSpin-transfer torque magnetic random access memory (STT-MRAM) based computation-in-memory (CIM) architectures have shown great prospects for an energy-efficient computing. However, device variations and non-idealities narrow down the sensing margin that severely impacts the computing accuracy. In this work, we propose an adaptive referencing mechanism to improve the sensing margin of a CIM architecture for boolean binary logic (BBL) operations. We generate reference signals using multiple STT-MRAM devices and place them strategically into the array such that these signals can address the variations and trace the wire parasitics effectively. We have demonstrated this behavior using an STT-MRAM model, which is calibrated using 1Mbit characterized array. Results show that our proposed architecture for binary neural networks (BNN) achieves up to 17.8 TOPS/W on the MNIST dataset and 130× performance improvement for the text encryption compared to the software implementation on Intel Haswell processor. Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory
No full textEmerging non-volatile resistive memories like Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) and Resistive RAM (RRAM) are in the focus of today’s research. They offer promising alternative computing architectures such as computation-in-memory (CiM) to reduce the transfer overhead between CPU and memory, usually referred to as the memory wall, which is present in all von Neumann architectures. A multitude of architectures with CiM capabilities are based on these devices, due to their inherent resistive behavior and thus their ability to perform calculation directly within the memory, and thus without invoking the CPU at all. However, emerging memories are sensitive to Process, Voltage and Temperature (PVT) variations. This sensitivity has an even larger impact on CiM architectures. In this paper, we analyze and compare the impact of PVT variations on STT-MRAM and RRAM-based CiM architectures. We perform a sensitivity analysis to identify which parts of the CiM structure are most susceptible to PVT variations, for each technology. Based on these analyses, we recommend that STT-MRAM is used in high-performance CiM, while RRAM is used for edge CiM.Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
Device-Aware Test for Back-Hopping Defects in STT-MRAMs
No full textThe development of Spin-transfer torque magnetic RAM (STT-MRAM) mass production requires high-quality dedicated test solutions, for which understanding and modeling of manufacturing defects of the magnetic tunnel junction (MTJ) is crucial. This paper introduces and characterizes a new defect called Back-Hopping (BH); it also provides its fault models and test solutions. The BH defect causes MTJ state to oscillate during write operations, leading to write failures. The characterization of the defect is carried out based on manufactured MTJ devices. Due to the observed non-linear characteristics, the BH defect cannot be modelled with a linear resistance. Hence, device-aware defect modeling is applied by considering the intrinsic physical mechanisms; the model is then calibrated based on measurement data. Thereafter, the fault modeling and analysis is performed based on circuit-level simulations; new fault primitives/models are derived. These accurately describe the way the STT-MRAM behaves in the presence of BH defect. Finally, dedicated march test and a Design-for-Test solutions are proposed.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
On the impact of supply voltage variation on the statistical reliability of a Spin-transfer-torque MRAM (STT-MRAM)
No full textThe Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) presents as a promising alternative to today embedded memories due to its reduced read/write latency and high integration capability. Today aggressive technology scaling requirements, affects also the STT-MRAM by means of fabrication induced process variability and aging phenomena. These issues make reliability prediction a major concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory. The reliability prediction is performed at cell level, accounting for fabrication induced variability and aging phenomena simultaneously affecting the nMOS and MTJ devices. In addition, the effect of supply voltage variation on the cell reliability is also studied. The results show that a negative variation of the supply voltage highly degrades the cell reliability
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design
No full textThe popularity of perpendicular magnetic tunnel junction (pMTJ)-based spin-transfer torque magnetic random access memories (STT-MRAMs) is growing very fast. The performance of such memories is very sensitive to magnetic fields, including both internal and external ones. This article presents a magnetic-field-aware compact model of pMTJ, named the MFA-magnetic tunnel junction (MTJ) model, for magnetic/electrical co-simulation of MTJ/CMOS circuits. Magnetic measurement data of MTJ devices, with diameters ranging from 35 to 175 nm, are used to calibrate an in-house magnetic coupling model. This model is subsequently integrated into our developed compact pMTJ model, which is implemented in Verilog-A. The superiority of the proposed MFA-MTJ model for device/circuit co-design of STT-MRAM is demonstrated by simulating a single pMTJ as well as STT-MRAM full circuits. The design space is explored under PVT variations and various configurations of magnetic fields.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
Monitoring Yearly Change Patterns of the Surface Tidal Trail (STT) in Tidal Flats: A Novel Morphological Indicator Extracted from a Near-Infrared Terrestrial Laser Scanner
No full textTidal flats play an important role in the geomorphological and biological dynamics of coasts. Research on the morphological evolution of tidal flats constitutes one of the key research issues pertaining to the sustainability of coastal ecosystems and related coastal defense issues. In this work, a novel indicator, the surface tidal trail (STT), was extracted from a near infrared terrestrial laser scanner and studied. The results show that the area intensity and size of STTs decline yearly. Meanwhile, the position shift of the peak value on the STT curves presents a similar pattern of hydrodynamic force in response to the seawall, which has been studied in previous works. Although no direct correlation between the STT intensity and the deposition rate was found, the corresponding hydrodynamic force data were not available in this work. The change process of STTs still provides a possible speculation that hydrodynamic force and the softness of tidal surfaces are two main factors that form and influence STTs. For future research, establishing the direct quantitative relationships among hydrodynamic force, topography, and STTs on different temporal and spatial scales would help to better understand this novel indicator.Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Coastal EngineeringHydraulic Engineerin
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