1,721,042 research outputs found
Design Methods and Tools for Nanocomputing: from Silicon Nanoarrays to Nano Magnetic Logic
No full textComplementary metal-oxide semiconductor (CMOS) technology has driven the electronic scenario for the last 40 years. The exponential grow of computing power implicates technological challenges, such as scaling transistor sizes, increasing clock frequency and reducing the power consumption. These goals raise dramatically the manufacturing cost with every new technology node. The projections of the ITRS roadmap report tell us that the scaling will be also influenced by fundamental physical limits. These observations have stimulated researchers from industry and academia to investigate possible feasible alternatives to CMOS technology. Since at the time of writing is difficult to find a clear winner, many possibilities are studied. They are based on different computational variables such as charge controlled (i.e. transistors) or magnetic field controlled devices. But, all of them have three aspects in common: i) the manufacturing process is still not mature, so they have to deal with a high defect rate; ii) the high density expected from these new devices arise problems related to the design automation field; iii) currently no tools, specifically targeted for emerging devices, are available on the market that allow researchers to investigate these technologies. In fact, it is rather difficult to find a toolchain of existing software able to provide a complete design flow from nanodevice simulation to floorplanning, place and route, and nanoarchitecture simulation and evaluation, able to handle emerging devices related constraints. This manuscript focuses on the development of a CAD tool for nanotechnologies, named ToPoliNano. It has the ability, starting from the VHDL description of the circuit, to automatically generate the physical layout choosing a target nanotechnology. At the time of writing two technologies are supported: silicon nanorrays and in-plane NanoMagnetic Logic. After the layout phase, the user can simulate the circuit behavior with an integrated simulation engine. In this work, three beyond CMOS technologies are investigated and analyzed from an architectural point of view. The first one is based on silicon nanoarrays, the last two come from the Quantum dot Cellular Automata (QCA) family, the in-plane Nano Magnetic Logic (iNML) and the perpendicular Nano Magnetic Logic (pNML). The aim of this thesis is to analyze the layout constrains of these emerging technologies making an architectural exploration. The investigation and the benchmarking is enabled thanks to ToPoliNano, which has been enriched, during my PhD, of a place and route engine and a fault injection mechanism to verify circuits robustness. These features implementation will be discussed more in detail respectively in part 2 and 1. After a brief technological background provided in the introduction, the thesis is divided in three main parts dedicated to the three technologies analyzed: silicon nanoarray, iNML and pNML. In part 1 the high defect rate of silicon nanoarray technology is discussed and analyzed in order to find a method to design more reliable circuits. A new methodology has been developed and tested through our CAD tool ToPoliNano. Fault tolerant circuits have been tested injecting different fault maps and evaluating the output error rate and yield. In part 2, the main working structure of the layout engine and the layout constraints of iNML technology are introduced. In part 2, first the main working principle and the layout constrains are presented to the reader. Then, a detailed description of the design flow implemented in ToPoliNano will be presented. The place and route engine implemented in ToPoliNano will be analyzed and described in detail with examples. The algorithms are compared and results are provided in the last part of this section. In the last part, the pNML technology will be analyzed. In particular, this work has been done in collaboration with the
vlsi-nanocomputing/risc-v-lim-architecture: version-1.0.0
No full textThe aim of the project is to propose a RISC-Vlim microprocessor that supports Logic-in-Memory operations. The RISC-Vlim is based on the RISC-V ISA where the data memory is replaced with a memory capable of doing simple operations on the data stored inside it. The preliminary results demonstrate how the use of such memories can improve the algorithm execution speed, reducing the need for complex solutions and saving energy.
The project uses the available RISC-V IP and the Logic-in-memory concept in order to improve the average execution time of the RISC-V memory operations and then reduce the overall execution time in programs. The goal has been reached by introducing a new memory model, capable to perform logic operations additionally to the simple reads or writes. To exploit this new memory capability the RISC-V ISA has been enlarged
Nanomagnetic Logic: From Devices to Systems
Full text linkA digital computing system with ferromagnets as switches, magnetic stray
fieds for computation, and domain walls for information transport — is it a curios-
ity or ready for ultra-large-scale-integration? Over the last decade, starting from
sub-micrometer sized Nanomagnets comprised of Co/Pt multilayers, a functionally
complete set of logic gates and memory elements were experimentally demonstrated
as a potential co-processing unit for CMOS microprocessors called perpendicular
Nanomagnetic Logic (pNML). From the beginning of this endeavor, not only sin-
gle devices but investigations of complex circuits like full-adders and multiplexers
finally culminated in an EDA tool called ToPoliNano. It offers a complete design
flow for system-level exploration of field coupled technologies, including pNML. In
particular, its layout editor MagCAD provides the possibility to design, simulate and
re-use pNML modules in larger architectures. The underlying compact models are
continuously adapted to newest developments in pNML technology, e.g. improve-
ments in materials, device design and exploitation of novel physical effects. With
that, efficient and reliable benchmarking against CMOS implementations is possible,
and important system level aspects are directly fed back to the technology and device engineers
A Machine Learning Approach for Queen Bee Detection Through Remote Audio Sensing to Safeguard Honeybee Colonies
Full text linkHoneybees play a pivotal role in maintaining global ecosystems and agricultural productivity through their indispensable contribution to crop pollination. However, the alarming rise in honeybee mortality, attributed to various stress factors including climate change, has highlighted the urgency of implementing effective monitoring strategies. Remote sensing of beehives emerges as a promising solution, with a focus on understanding and mitigating the impacts of these stressors. Differently from other approaches proposed in the literature, this study specifically explores the potential of lightweight machine learning models and the extraction of compressed feature to enable future deployment on microcontroller devices. The experimentation involves the application of support vector machines and neural network classifiers, considering the influence of variable audio chunk durations, the utilization of different hyperparameters and combining the audio recorded in several hives and available in different datasets
Design of a system to be used in clinical contexts for the reproduction of ecological audiovisual scenes aimed at hearing assistive devices users
Full text linkAlthough the continuous advancements of devices for auditory assistance, it is still a fact that they often are not as supportive as needed. Many users complain of poor benefits felt from these devices when used in more acoustically complex real-world conditions, such as one-to-one or multiple-talker conversations inside time-varying noisy environments with adverse room acoustics. One causing factor is the inefficacy of in-laboratory and in-field listening tests currently used to predict the real-life impact of hearing disorders during the execution of hearing assistive devices fitting. While the former lacks ecological validity and visual cues, the latter lacks repeatability of the tested conditions. In order to close the gap between these methods, hearing research has started exploiting virtual reality (VR) to auralize complex acoustic environments (CAEs) where hearing assistive devices could be tested. This project proposes the development of a system to perform ecological auditory tests that can be easily replicated and used inside clinical contexts, through which the clinicians can create customized audiovisual scenes where speech intelligibility tests are auralized inside multiple CAEs with different noise types and positions. The system is installed inside a small sound-insulated room and mainly consists of a spherical array of 16 active loudspeakers synchronized with a VR headset to reproduce immersive 3D - 360° audiovisual scenes. The acoustical scenes are collected in-field through 3rd order ambisonics recordings of room impulse responses using the Zylia ZM-1 microphone. The visual scenes are taken through 3D and 2D footage with different resolutions using either the 8K Insta360 Pro or the 4K Insta360 ONE X2 camera. The implementation of objective and perceptual tests on normal hearing subjects is planned to evaluate the system reproduction accuracy compared with real environments and the degree of plausibility, sense of presence and immersion. Eventually, the system will be validated on hearing-impaired subjects
Incremental firmware update over-the-air for low-power IoT devices over LoRaWAN
Full text linkRemote firmware updates in Internet of Things (IoT) devices remain a major challenge due to the constraints of many IoT communication protocols. In particular, transmitting full firmware images over low-bandwidth links such as Long Range Wide Area Network (LoRaWAN) is often impractical. Existing techniques, such as firmware partitioning, can alleviate the problem but are often insufficient, especially for battery-powered devices where time and energy are critical constraints. Consequently, physical maintenance is still frequently required, which is costly and impractical in large-scale deployments. In this work, we introduce bpatch, a lightweight method for generating highly compact delta patches that enable on-device firmware reconstruction. The algorithm is explicitly designed for low-power devices, minimizing memory requirements and computational overhead during the update process. We evaluate bpatch on 173 firmware images across three architectures. Results show that it reduces update payloads by up to 39,000x for near-identical updates and by 9–18x for typical minor revisions, eliminating the need to transmit full firmware images. Experimental results further demonstrate significant time and energy savings, with performance comparable to more complex alternatives. bpatch is released as open-source and, although demonstrated on LoRaWAN, the approach is flexible and can be adapted to other IoT communication technologies
Enabling fully connected probabilistic computing through a fast pipelined multi-operand adder
No full textProbabilistic computing has gained a prominent role as combinatorial optimization solvers on classical hardware. Probabilistic bits (pbits) must be updated sequentially to rapidly converge to the lowest energy state of the objective function. Yet, all the current implementations rely on mappings to sparse graphs to speed up the update operation. In this paper, we present a new pipelining technique for a multi-operand adder to enable a fully connected structure of the pbit native graph. Previous approaches lack a pipelined architecture and avoid data dependencies by updating each pbit only after all its connected pbits are updated. This results in a small adder but limits execution to sparse problems and implies a prominent supplement of pbits due to sparsification. Our implementation uses a fast pipelined adder that receives new operands at each pipe stage, handling data dependencies during execution. The pipelined unit was evaluated against other pipeline strategies and state-of-the-art emulator implementations, demonstrating promising pbits update times. The obtained performance closely matches implementations on sparse graphs, implying greater scalability, especially for denser problems. With a future parallelized architecture, this may enable fast probabilistic computing for fully connected problems, avoiding a significant or even unacceptable increase in the number of required pbit
Testing Nanoarrays Fault Tolerance
Full text linkThe interesting expectations on nanoarray based
circuits are counterbalanced by critical issues related to reliability.
Nanowires and active devices currently cannot rely on a mature
technology and high rates of defects are still to be expected.
Our approach to evaluate the effects on nanoarray based circuits
behavior consists in simulating at switch level the precise behavior
of the circuit considering a statistical distribution of faults
throughout the tile area. We are able to reckon the output error
rate of nanoarray circuits as a function of defective rates and
defect distribution giving to both technologists and architects
directions to find possible solutions
Advancing Beekeeping: IoT and TinyML for Queen Bee Monitoring Using Audio Signals
Full text linkBeekeeping plays an essential role in maintaining ecosystems through pollination and enhancing biodiversity. The presence of the queen bee inside the hive is an important indicator for the health of the bee colony. Monitoring the health of honeybees and their hives is crucial not only for bees but also for the entire ecosystem. This article introduces a tiny machine learning (ML) application for edge computing in the Internet-of-Things (IoT) systems, designed to predict the queen bee's presence. The solution, implemented on a low-power microcontroller (MCU), listens to the sound produced by honeybees and aids beekeepers by automating health assessments of the colony. The system utilizes audio recordings of honeybees combined with artificial intelligence (AI) techniques, while the second focuses on optimizing a feature extraction algorithm from these recordings to minimize latency and energy use in the IoT setup. The findings show that despite the implementation of a simpler ML model and audio preprocessing with lower computational precision, the final metrics remain comparable to those analyzed, with only a limited reduction
An Integrated Multi-Sensor System for Remote Bee Health Monitoring
Full text linkOver 75% of the world's food crops depends on pollination and in particular by the inestimable value of the service provided by bees. Besides, the bee colony health is a good indicator of the quality of the environment and it is strongly affected by many aspects such as beekeepers' management practices, policies adopted for cropping and land use. However, the climate change, the intensive agriculture, pesticides, biodiversity loss, Varroa mites and pollution are the leading cause of bees death world wide. The role of beekeepers is of extremely importance to mitigate this damage. Apiaries are usually located in remote environment an require frequent visit by the beekeepers. Indeed, the beekeeping sector lacks of suitable tools for risk assessment and decision making that can be used by stakeholders. Smart monitoring systems assessing the health of the colony and the honey production would be beneficial for such community. In this work, we present a prototype of an embedded multi-sensor system for beehive monitoring with the aim of providing a simple solution to beekeepers. Indeed, the proposed system do not require modification of the beehive and it is compact enough to be simply inserted in the brood box. It measures the vital parameters of the beehive, such as temperature, weight, humidity and CO2 concentration. It exploits the low power communication protocol LoRaWAN for the data transmission. The collected data are made available to the beekeeper through a web application. We show the effectiveness of such compact, non-invasive embedded system with its installation in an apiary
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