1,721,060 research outputs found
On the origin of the dispersion of erased threshold voltages in flash eeprom memory cells
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Modelling temperature effects in the DC I-V characteristics of GaAs MESFETs
No full textThis paper presents a simple model to account for the main temperature effects influencing the dc performance of GaAs MESFET's. The model is based on a consistent solution of heat flow and current equations, that accounts for nonuniform power dissipation within the device. The simulation results are satisfactorily compared with experimental data obtained with pulsed and dc measurements performed on conventional devices as well as on suitable test structures
Frequency Resolved Measurements for the Characterization of MOSFET Parameters at Low Longitudinal Fields
No full textA new technique is presented to extract the main parameters required for transistor modeling at low longitudinal fields (parasitic resistance, intrinsic conductivity factor, threshold voltage, and body factor k) from a single MOSFET. The method makes use of easy-to-perform ac frequency-resolved measurements to overcome repeatability and accuracy problems encountered with de data. The technique has been satisfactorily validated on MOSFET's down to 0.8 mu m channel length
A novel method to determine the Source and Drain resistances of individual MOSFETs
No full textA novel method is presented to determine the bias-dependent series resistances and intrinsic conductance factor of individual MOSFETs. The parameter-extraction procedure can also be applied to groups of scaled transistors to work out the device effective channel length. The method is derived analytically from the conventional theory of ideal MOSFETs, and the deviations of real devices from such a case are studied using two-dimensional device simulations. Experimental results with n- and p-channel conventional and LDD (lightly doped drain) MOSFETs are presented to demonstrate the correctness of the metho
Fault simulation of parametric bridging faults in CMOS IC's
No full textThe fault simulation of resistive bridging faults inside complex CMOS macro-gates requires proper evaluation of resistances, in order to correctly determine realistic fault coverages. To this purpose, the present work illustrates a novel approach applicable to a large category of faults (bridgings, transistor stuck-ons and node stuck-ats) giving rise to resistive paths between power supply and ground, hence being all indicated by the general term of “bridging faults.” Such a method, avoiding single-fault injection procedure, consists of a fault analysis performed inside macro-gates aimed at determining the threshold resistance discriminating whether or not a given fault is detectable as a logic error; this analysis is performed inside CMOS macro-gates whose output is observable, as determined by means of any method and/or simulator. Finally, to fully characterize the quality of a test sequence with regard to resistive bridging faults, a new definition of fault coverage is presented, because the common concept of fault detection is not applicable to parametric faults. © 1993 IEE
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