1,720,996 research outputs found
HyBloSE: Hybrid blockchain for secure-by-design smart environments
No full textAlthough smart environments are a key component of the Internet of Things (IoT), it is also clear that billions connected doors, washing machines, ovens and others will ultimately raise security and privacy concerns. Early work in this area, as well as most of commercial solutions, has adopted a centralized client/server approach, neglecting the multitude of risks that are induced by an unfair control of the server side. This has made the adoption of a decentralized and trust-less framework quintessential to guarantee devices security. Nevertheless, decentralized proposals are hardly applicable due to costs, slowness and privacy issues. In this paper, we make the use of blockchain practical for smart environments by designing HyBloSE, a secure-by-design and lightweight blockchain-based framework, able to run on low-power devices without additional hardware. HyBloSE is built by using Delegated Proof of Authority and a Moving Window Blockchain. We evaluate HyBloSE through a network emulator and real experiments with different Raspberry Pi platforms. Results show that HyBloSE guarantees a higher security level in terms of resiliency to internal and external attacks compared to centralized solutions, with overhead below 0.38s per operation and less than $4 per month for unlimited operations. Furthermore, we show how Proof of Authority is more adapt then Proof of Work in IoT private scenarios
BFA-Sense: Learning Beamforming Feedback Angles for Wi-Fi Sensing
No full textIn this paper, we propose BFA-Sense, a completely novel approach to implement standard-compliant Wi-Fi sensing applications. Wi-Fi sensing enables game-changing applications in remote healthcare, home entertainment, and home surveillance, among others. However, existing work leverages the manual extraction of the uncompressed channel state information (CSI) from Wi-Fi chips, which is not supported by the 802.11 standard-compliant devices and hence requires the use of specialized equipment. On the contrary, BFA-Sense leverages the compressed beamforming feedback angles (BFAs) transmitted during the standard-compliant sounding procedure to characterize the propagation environment. Conversely from the uncompressed CSI, BFAs (i) can be recorded without any firmware modification, and (ii) allows a single monitor device to simultaneously capture the channels between the access point and all the stations, thus providing much better sensitivity. We evaluate BFA-Sense through an extensive data collection campaign with three subjects performing twenty different activities in three different environments. We assess the cross-domain adaptability of BFA-Sense through embedding learning for tackling unseen environments with a few samples from the new environment. The results show that the proposed BFAs-based approach achieves about 11% more accuracy when compared to CSI-based prior work
Exposing the CSI: A Systematic Investigation of CSI-based Wi-Fi Sensing Capabilities and Limitations
No full textThanks to the ubiquitous deployment of Wi-Fi hotspots, channel state information (CSI)-based Wi-Fi sensing can unleash game-changing applications in many fields, such as healthcare, security, and entertainment. However, despite one decade of active research on Wi-Fi sensing, most existing work only considers legacy IEEE 802.11n devices, often in particular and strictly-controlled environments. Worse yet, there is a fundamental lack of understanding of the impact on CSI-based sensing of modern Wi-Fi features, such as 160-MHz bandwidth, multiple-input multiple-output (MIMO) transmissions, and increased spectral resolution in IEEE 802.11ax (Wi-Fi 6). This work aims to shed light on the impact of Wi-Fi 6 features on the sensing performance and to create a benchmark for future research on Wi-Fi sensing. To this end, we perform an extensive CSI data collection campaign involving 3 individuals, 3 environments, and 12 activities, using Wi-Fi 6 signals. An anonymized ground truth obtained through video recording accompanies our 80-GB dataset, which contains almost two hours of CSI data from three collectors. We leverage our dataset to dissect the performance of a state-of-The-Art sensing framework across different environments and individuals. Our key findings suggest that (i) MIMO transmissions and higher spectral resolution might be more beneficial than larger bandwidth for sensing applications; (ii) there is a pressing need to standardize research on Wi-Fi sensing because the path towards a truly environment-independent framework is still uncertain. To ease the experiments' replicability and address the current lack of Wi-Fi 6 CSI datasets, we release our 80-GB dataset to the community
Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms
Full text linkThis work focuses on the time-predictable execution of Deep Neural Networks (DNNs) accelerated on FPGA System-on-Chips (SoCs). The modern DPU accelerator by Xilinx is considered. An extensive profiling campaign targeting the Zynq Ultrascale+ platform has been performed to study the execution behavior of the DPU when accelerating a set of state-of-the-art DNNs for Advanced Driver Assistance Systems (ADAS). Based on the profiling, an execution model is proposed and then used to derive a response-time analysis. A custom FPGA module named DICTAT is also proposed to improve the predictability of the acceleration of DNNs and tighten the analytical bounds. A rich set of experimental results based on both analytical bounds and measurements from the target platform is finally presented to assess the effectiveness and the performance of the proposed approach on ADAS applications
TOP: Towards Open & Predictable Heterogeneous SoCs
Full text linkEnsuring predictability in modern real-time Systems-on-Chip (SoCs) is an increasingly critical concern for many application domains such as automotive, robotics, and industrial automation. An effective approach involves the modeling and development of hardware components, such as interconnects and shared memory resources, to evaluate or enforce their deterministic behavior. Unfortunately, these IPs are often closed-source, and these studies are limited to the single modules that must later be integrated with third-party IPs in more complex SoCs, hindering the precision and scope of modeling and compromising the overall predictability. With the coming-of-age of open-source instruction set architectures (RISC-V) and hardware, major opportunities for changing this status quo are emerging. This study introduces an innovative methodology for modeling and analyzing State-of-the-Art (SoA) open-source SoCs for low-power cyber-physical systems. Our approach models and analyzes the entire set of open-source IPs within these SoCs and then provides a comprehensive analysis of the entire architecture. We validate this methodology on a sample heterogenous low-power RISC-V architecture through RTL simulation and FPGA implementation, minimizing pessimism in bounding the service time of transactions crossing the architecture between 28% and 1%, which is considerably lower when compared to similar SoA works
AXI HyperConnect: A predictable, hypervisor-level interconnect for hardware accelerators in FPGA SoC
No full textFPGA-based system-on-chips (SoC) are powerful computing platforms to implement mixed-criticality systems that require both multiprocessing and hardware acceleration. Virtualization via hypervisor technologies is, de-facto, an effective technique to allow the co-existence of multiple execution domains with different criticality levels in isolation upon the same platform. Implementing such technologies on FPGA-based SoC poses new challenges: one of such is the isolation of hardware accelerators deployed on the FPGA fabric that belong to different domains but share common resources such as a memory bus. This paper proposes AXI HyperConnect, a hypervisor-level hardware component that allows interconnecting hardware accelerators to the same bus while ensuring isolation and predictability features. AXI HyperConnect has been implemented on modern FPGA-SoC by Xilinx and tested with real-world accelerators, including one for Deep Neural Network inference
Modeling and analysis of bus contention for hardware accelerators in FPGA SoCs
No full textFPGA System-on-Chips (SoCs) are heterogeneous platforms that combine general-purpose processors with a field-programmable gate array (FPGA) fabric. The FPGA fabric is composed of a programmable logic in which hardware accelerators can be deployed to accelerate the execution of specific functionality. The main source of unpredictability when bounding the execution times of hardware accelerators pertains the access to the shared memories via the on-chip bus. This work is focused on bounding the worst-case bus contention experienced by the hardware accelerators deployed in the FPGA fabric. To this end, this work considers the AMBA AXI bus, which is the de-facto standard communication interface used in most the commercial off-the-shelf (COTS) FPGA SoCs, and presents an analysis technique to bound the response times of hardware accelerators implemented on such platforms. A fine-grained modeling of the AXI bus and AXI interconnects is first provided. Then, contention delays are studied under hierarchical bus infrastructures with arbitrary depths. Experimental results are finally presented to validate the proposed model with execution traces on two modern FPGA-based SoC produced by Xilinx (Zynq-7000 and Zynq-Ultrascale+ families) and to assess the performance of the proposed analysis
PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms
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