64 research outputs found
Retracted article: Retinal photoreceptors targeting SA-<i>g</i>-AA coated multilamellar liposomes carrier system for cytotoxicity and cellular uptake evaluation
No full textWe, the Editor and Publisher of the Journal of Liposome Research, have retracted the following article: E.R. Anishiya Chella Daisy, Naresh Kumar Rajendran, Murugaraj Jeyaraj, Andy Ramu, Mariappan Rajan (2021). Retinal photoreceptors targeting SA-g-AA coated multilamellar liposomes carrier system for cytotoxicity and cellular uptake evaluation. Journal of Liposome Research, 31: 2, 203–216, DOI: 10.1080/08982104.2020.1768111 After publication of this article, concerns about duplication of part of Figure 3B in Figure 3A were brought to the attention of the Editor and Publisher. The authors were contacted and while they did provide a replacement image, they were unable to provide the replacement image or the original images in a format that satisfies our requirements to confirm its authenticity. We have been informed in our decision-making by our policy on publishing ethics and integrity and the COPE guidelines on retractions. The retracted article will remain online to maintain the scholarly record, but it will be digitally watermarked on each page as ‘Retracted’.</p
Clock multiplication techniques for high-speed I/Os
No full textGeneration of a low-jitter, high-frequency clock from a low-frequency reference clock using classical analog phase-locked loops (PLLs) requires a large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. In this dissertation different clock multiplication techniques have been explored that can be suitable for high-speed wireline systems. With the emphasis on ring oscillator based architecture using cascaded stages, three possible architectures are explored.
First, a scrambling TDC (STDC) is presented to improve deterministic jitter (DJ) performance when used with a low-frequency reference clock. A cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage is used to achieve low random jitter in a power efficient manner. Fabricated in a 90nm CMOS process, the prototype frequency synthesizer consumes 4.76mW power from a 1.0V supply and generates 160MHz and 2.56 GHz output clocks from a 1.25MHz crystal reference frequency. The long-term absolute jitter of the 60MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 psrms and 4.18 psrms, while the peak-to-peak jitter is 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz.
Second, a hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator-based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into an XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with an in-band phase noise floor of -104 dBc/Hz and 1.5 psrms integrated jitter. The clock multiplier achieves power efficiency of 2.4mW/GHz and FoM of -225.8 dB.
Finally, an efficient clock generation, recovery, and distribution techniques for flexible-rate transceivers are presented. Using a fixed-frequency low-jitter clock provided by an integer-N PLL, fractional frequencies are generated/recovered locally using multi-phase fractional clock multipliers. Fabricated in a 65nm CMOS, the prototype transceiver can be programmed to operate at any rate from 3-to-10 Gb/s. At 10 Gb/s, integrated jitter of the Tx output and recovered clock is 360 fsrms and 758 fsrms, respectively.Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2019-05-01The student, Romesh Kumar Nandwana, accepted the attached license on 2017-04-17 at 15:09.The student, Romesh Kumar Nandwana, submitted this Dissertation for approval on 2017-04-17 at 15:42.This Dissertation was approved for publication on 2017-04-19 at 08:46.DSpace SAF Submission Ingestion Package generated from Vireo submission #10816 on 2017-08-10 at 15:05:48Made available in DSpace on 2017-08-10T20:32:59Z (GMT). No. of bitstreams: 3
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Energy-efficient wireline transceivers
No full textPower-efficient wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are expected to be fully integrated. This thesis explores enabling techniques to implement such transceivers in both circuit and system levels. Specifically, three prototypes will be presented: (1) a 5Gb/s reference-less clock and data recovery circuit (CDR) using phase-rotating phase-locked loop (PRPLL) to conduct phase control so as to break several fundamental trade-offs in conventional receivers; (2) a 4-10.5Gb/s continuous-rate CDR with novel frequency acquisition scheme based on bang-bang phase detector (BBPD) and a ring oscillator-based fractional-N PLL as the low noise wide range DCO in the CDR loop; (3) a source-synchronous energy-proportional link with dynamic voltage and frequency scaling (DVFS) and rapid on/off (ROO) techniques to cut the link power wastage at system level. The receiver/transceiver architectures are highly digital and address the requirements of new receiver architecture development, wide operating range, and low power/area consumption while being fully integrated. Experimental results obtained from the prototypes attest the effectiveness of the proposed techniques.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-12-01The student, Guanghua Shu, accepted the attached license on 2016-09-28 at 11:50.The student, Guanghua Shu, submitted this Dissertation for approval on 2016-09-28 at 15:42.This Dissertation was approved for publication on 2016-09-30 at 13:20.DSpace SAF Submission Ingestion Package generated from Vireo submission #10172 on 2017-02-28 at 14:40:52Made available in DSpace on 2017-03-01T17:00:54Z (GMT). No. of bitstreams: 3
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Women’s Entrepreneurship in Patriarchal Societies: The Case of Women’s Cooperatives in Turkey
No full textThis chapter explores the limits of and prospects for women’s entrepreneurship in patriarchal communities. The chapter investigates the patriarchal institutions and societal norms which work against women’s entrepreneurial activities and women’s presence in socioeconomic life in general. It also delves into women’s strategies to bargain, deal, and cope with patriarchal norms and institutions. The research is based on an extensive fieldwork on the case of Turkey, a country replete with patriarchal norms and institutions. The author conducts in-depth semi-structured interviews with members of women’s cooperatives throughout Turkey to better understand and explain the obstacles against women’s entrepreneurship in patriarchal societies and how women deal with these obstacles in their daily, entrepreneurial practices. In light of the fieldwork findings, the chapter concludes with policy implications and recommendations for more egalitarian and prosperous societies
Design of energy efficient high speed I/O interfaces
No full textThe student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs.
A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively.
Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers.
We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-05-01The student, Mrunmay Vyankatesh Talegaonkar, submitted this Dissertation for approval on 2016-03-11 at 14:46.This Dissertation was approved for publication on 2016-03-15 at 08:51.DSpace SAF Submission Ingestion Package generated from Vireo submission #9102 on 2016-07-07 at 14:16:14Made available in DSpace on 2016-07-07T21:14:23Z (GMT). No. of bitstreams: 3
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Low-area and power-efficient on-chip clock reference generation
No full textEmbargo set by: Seth Robbins for item 115686
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Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemAuthor requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemU of I OnlyThe advancement of modern one-chip applications, including system-on-chips (SoCs) and ultra-low-power systems such as wearables and internet-of-things (IoTs), has been the major driving force for the development of the integrated circuit industry over the past decade. One-chip reference generators are required by one-chip applications such as biomedical sensors, micro-controller units (MCUs), as well as high-speed input/output interfaces in SoCs. In addition to the power and volume constraints to ensure low-cost realization, one-chip applications typically operate across a wide range of frequencies, imposing challenging design requirements on the on-chip clock generators which are critical in timing coordination of the system. With aggressive scaling of the silicon technology improving transistor density of synthesized digital processors, clock generations with intensive analog/mixed-signal implementations have imposed obstacles to the overall scaling of power supply level, negating the overall benefits brought by the process scaling. This dissertation explores design techniques at both architecture and circuit level to achieve power- and volume-efficient designs without compromising the performance.
In the first project, we propose an alternative integral path control using time-based techniques in type-II PLL. Leveraging the inherent integration from frequency to phase via a ring oscillator, the time-based integral loop eliminates the passive capacitor of the loop filter in conventional architecture, achieving a highly digital implementation that scales favorably with more advanced process. A prototype time-based PLL is implemented using a ring oscillator-based integrator (ROI). Fabricated in 65 nm CMOS LP process, the prototype PLL occupies an active area of only 0.0021 mm2 and operates across a supply voltage range of 0.6 V to 1.2 V, providing output frequencies ranging from 0.4 to 2.6 GHz. At 2.2 GHz output frequency, the PLL consumes 1.82 mW at 1 V supply voltage, and achieves 3.73 psrms integrated jitter. This translates to an FoMJ of -226.0 dB, which compares favorably with state-of-the-art designs while occupying the smallest reported active area.
Next, we investigate the clock generators for ultra-low-power (ULP) systems for internet-of-thing (IoT) applications. RC relaxation oscillators (RCOs) are shown to achieve excellent frequency stability when generating clocks in kHz-MHz range, but are not very power efficient (5 μW/MHz). Their power efficiency further degrades at higher frequency due to additional complexity to maintain temperature stability, limiting the applications for MCUs operating at hundreds of MHz. Hence, we propose to use a ring oscillator (RO) based digital PLL to multiply the RCO frequency to the desired operating frequencies. Inherently, RO shows superior phase noise performance and power efficiency over RCO, and the PLL loop bandwidth needs to be lowered in order to mitigate the noise contribution from the RCO. Consequently, the output RO dominates the output clock phase noise beyond the bandwidth. To achieve a power efficient design, hybrid PLL architecture is employed with varactor-based analog proportional control and digital integral control using delta-sigma modulator (DSM) DAC. Switched resistor technique is employed to implement post-loop filter for DSM DAC in an area-efficient manner. Fabricated in 65 nm CMOS technology, the prototype HPLL achieves 2.3 psrms period jitter at 70 MHz and consumes 406 _W. The output oscillator evaluates to an excellent FoM of >162 dB across wide range of frequency from 45 to 75 MHz.
Finally, we address the area consumption for low-bandwidth PLL applications. In conventional type-II PLL architecture, reducing the bandwidth is achievable through drastic scaling of proportional path gain, which degrades the tracking capability of the PLL. On the other hand, the loop filter capacitor inevitably increases in order to maintain loop stability, consequently increasing the overall chip area consumption in low-bandwidth setting. To address the challenges observed in conventional PLL, we propose an alternative DPLL architecture using delay modulating clock buffer, which reduces the closed-loop bandwidth with the same hardware complexity of a conventional DPLL counterpart. Such architecture is particularly suitable in applications with RCO as the reference clock, as the DPLL is capable of operating directly with the internal capacitor charging node of RCO. Fabricated in 65 nm CMOS process, the prototype DPLL generates 48-330 MHz output frequencies from a reference clock in the range of 0.5-5 MHz. The DPLL occupies an active area of 125 μm by 125 μm, and achieves ±0.33% period jitter while consuming 63.5 μW at an output frequency of 240 MHz. This translates to an excellent power efficiency of 0.26 μW/MHz at 0.8 V supply voltage, which compares favorably with the state-of-the-art.Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2022-05-01The student, Junheng Zhu, accepted the attached license on 2019-12-09 at 17:05.The student, Junheng Zhu, submitted this Dissertation for approval on 2019-12-09 at 17:17.This Dissertation was approved for publication on 2019-12-11 at 14:50.DSpace SAF Submission Ingestion Package generated from Vireo submission #14766 on 2020-08-25 at 17:26:18Made available in DSpace on 2020-08-26T23:51:19Z (GMT). No. of bitstreams: 3
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Toward realizing power scalable and energy proportional high-speed wireline links
No full textGrowing computational demand and proliferation of cloud computing has placed high-speed
serial links at the center stage. Due to saturating energy efficiency improvements over the
last five years, increasing the data throughput comes at the cost of power consumption. Conventionally, serial link power can be reduced by optimizing individual building blocks such as
output drivers, receiver, or clock generation and distribution. However, this approach yields
very limited efficiency improvement. This dissertation takes an alternative approach toward
reducing the serial link power. Instead of optimizing the power of individual building blocks,
power of the entire serial link is reduced by exploiting serial link usage by the applications.
It has been demonstrated that serial links in servers are underutilized. On average, they
are used only 15% of the time, i.e. these links are idle for approximately 85% of the time.
Conventional links consume power during idle periods to maintain synchronization between
the transmitter and the receiver. However, by powering-off the link when idle and powering
it back when needed, power consumption of the serial link can be scaled proportionally to
its utilization. This approach of rapid power state transitioning is known as the rapid-on/off
approach. For the rapid-on/off to be effective, ideally the power-on time, off-state power,
and power state transition energy must all be close to zero. However, in practice, it is very
difficult to achieve these ideal conditions. Work presented in this dissertation addresses these
challenges.
When this research work was started (2011-12), there were only a couple of research papers
available in the area of rapid-on/off links. Systematic study or design of a rapid power state
transitioning in serial links was not available in the literature. Since rapid-on/off with
nanoseconds granularity is not a standard in any wireline communication, even the popular
test equipment does not support testing any such feature, neither any formal measurement methodology was available. All these circumstances made the beginning difficult. However,
these challenges provided a unique opportunity to explore new architectural techniques and
identify trade-offs. The key contributions of this dissertation are as follows.
The first and foremost contribution is understanding the underlying limitations of saturating energy efficiency improvements in serial links and why there is a compelling need to
find alternative ways to reduce the serial link power.
The second contribution is to identify potential power saving techniques and evaluate the
challenges they pose and the opportunities they present.
The third contribution is the design of a 5Gb/s transmitter with a rapid-on/off feature.
The transmitter achieves rapid-on/off capability in voltage mode output driver by using
a fast-digital regulator, and in the clock multiplier by accurate frequency pre-setting and
periodic reference insertion. To ease timing requirements, an improved edge replacement
logic circuit for the clock multiplier is proposed. Mathematical modeling of power-on time
as a function of various circuit parameters is also discussed. The proposed transmitter
demonstrates energy proportional operation over wide variations of link utilization, and is,
therefore, suitable for energy efficient links. Fabricated in 90nm CMOS technology, the
voltage mode driver, and the clock multiplier achieve power-on-time of only 2ns and 10ns,
respectively. This dissertation highlights key trade-off in the clock multiplier architecture,
to achieve fast power-on-lock capability at the cost of jitter performance.
The fourth contribution is the design of a 7GHz rapid-on/off LC-PLL based clock multi-
plier. The phase locked loop (PLL) based multiplier was developed to overcome the limita-
tions of the MDLL based approach. Proposed temperature compensated LC-PLL achieves
power-on-lock in 1ns.
The fifth and biggest contribution of this dissertation is the design of a 7Gb/s embedded
clock transceiver, which achieves rapid-on/off capability in LC-PLL, current-mode transmit-
ter and receiver. It was the first reported design of a complete transceiver, with an embedded
clock architecture, having rapid-on/off capability. Background phase calibration technique in
PLL and CDR phase calibration logic in the receiver enable instantaneous lock on power-on.
The proposed transceiver demonstrates power scalability with a wide range of link utiliza-
tion and, therefore, helps in improving overall system efficiency. Fabricated in 65nm CMOS technology, the 7Gb/s transceiver achieves power-on-lock in less than 20ns. The transceiver
achieves power scaling by 44x (63.7mW-to-1.43mW) and energy efficiency degradation by
only 2.2x (9.1pJ/bit-to-20.5pJ/bit), when the effective data rate (link utilization) changes
by 100x (7Gb/s-to-70Mb/s).
The sixth and final contribution is the design of a temperature sensor to compensate
the frequency drifts due to temperature variations, during long power-off periods, in the
fast power-on-lock LC-PLL. The proposed self-referenced VCO-based temperature sensor
is designed with all digital logic gates and achieves low supply sensitivity. This sensor is
suitable for integration in processor and DRAM environments. The proposed sensor works
on the principle of directly converting temperature information to frequency and finally
to digital bits. A novel sensing technique is proposed in which temperature information
is acquired by creating a threshold voltage difference between the transistors used in the
oscillators. Reduced supply sensitivity is achieved by employing junction capacitance, and
the overhead of voltage regulators and an external ideal reference frequency is avoided. The
effect of VCO phase noise on the sensor resolution is mathematically evaluated. Fabricated
in the 65nm CMOS process, the prototype can operate with a supply ranging from 0.85V
to 1.1V, and it achieves a supply sensitivity of 0.034oC/mV and an inaccuracy of ±0.9oC
and ±2.3oC from 0-100oC after 2-point calibration, with and without static nonlinearity
correction, respectively. It achieves a resolution of 0.3oC, resolution FoM of 0.3(nJ/conv)res2 ,
and measurement (conversion) time of 6.5μs.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2017-12-01The student, Tejasvi Anand, accepted the attached license on 2015-11-20 at 13:54.The student, Tejasvi Anand, submitted this Dissertation for approval on 2015-11-20 at 14:12.This Dissertation was approved for publication on 2015-11-24 at 13:47.DSpace SAF Submission Ingestion Package generated from Vireo submission #8817 on 2016-03-02 at 14:13:14Made available in DSpace on 2016-03-02T21:06:34Z (GMT). No. of bitstreams: 2
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Previous issue date: 2015-11-24Embargo set by: Seth Robbins for item 91408
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