1,720,969 research outputs found
Towards Accelerated Transient Solvers for Full System Power Integrity Verification
Full text linkThis paper proposes a novel framework for power integrity verification of multicore systems, including voltage stabilization provided by multiple integrated voltage regulators at the core interfaces. The proposed framework adopts a two-stage macromodeling strategy to derive a compact representation of the full system dynamics as observed from each core. These dynamics are parameterized by the time-varying duty cycle provided by dedicated feedback controllers to each voltage regulator, here implemented through an averaged model. We show that the proposed simulation framework has the potential to outperform direct transient analysis based on SPICE engines
Structured Model Order Reduction of System-Level Power Delivery Networks
Full text linkThis paper proposes a comprehensive model order reduction framework to enable fast power integrity verification at the system level. This approach is developed to compress models of complete power delivery networks of high-end multiprocessor systems, where electromagnetic models of board and package are connected through banks of per-core Fully Integrated Voltage Regulators to chip models and loads in a closed-loop configuration. Due to complexity in both dynamical behavior and number of signals to be monitored, a direct transient simulation at the system level is very challenging. We show that a careful topological formulation of the circuit equations leads to a global model format that enables a structured projection framework for the elimination of the redundant states. Within this framework, we present and compare two alternative approaches based on approximate interpolation and empirical balancing, here adapted for the application at hand. In both cases, the resulting system is proven to be unconditionally stable both in open and in closed-loop configuration. Transient simulation of the reduced system provides a speedup exceeding 100× with respect to SPICE
Fully Integrated Voltage Regulators (FIVRs) with Package In-situ Coupled CoaxMIL Inductor for High Power Density Microprocessor Applications
No full textBalancing-Based Model Reduction for Fast Power Integrity Verification
Full text linkThis paper presents a novel Model Order Reduction approach as an extension of the well-known Balanced Truncation. The key contribution is a semi-analytical approach for the numerical evaluation of the Gramian matrices that are functional for optimal reduction of large-scale state-space systems. Appli- cation to product-level full-system Power Distribution Networks including integrated voltage regulation circuitry allows transient verification in more than 200× faster than SPICE
Enabling Full-System Transient Power Integrity Verification via Model Order Reduction and Waveform Relaxation
Full text linkWe present a comprehensive modeling and simulation framework for transient analysis of multicore power delivery networks equipped with integrated voltage regulator banks. Numerical simulation at the system level of such structures remains a challenging task due to the large-scale nature of the equations to be solved, combined with the nonlinearities of the regulator switches and the feedback loops of the corresponding controls. We propose a solution based on a combination of structure-pre-serving Model Order Reduction algorithms with parallel time-domain solvers based on system partitioning and Waveform Relaxation. Application to commercial mobile and enterprise server benchmarks demonstrates a speedup as much as 1000X with respect to HSPICE, with negligible loss of accuracy
A Structured Krylov Subspace Projection Framework for Fast Power Integrity Verification
Full text linkThis paper presents a model order reduction approach, specifically designed for the generation of compact and efficient transient simulation models of system-level power distribution networks (PDN) of multicore processor systems. The proposed approach applies a Krylov subspace projection, with a structure that is adapted to a block-coupled state-space description of individual PDN subsystems. The latter include board-package, averaged models of integrated voltage regulators switching circuitry, and individual models of all cores including regulator inductors and capacitors. Numerical results from pro-posed reduced-order models provide major speedup with respect to SPICE with negligible loss of accuracy
A Two-Level Waveform Relaxation Approach for System-Level Power Delivery Verification
Full text linkThis paper considers a complete power delivery network model of a multicore processing system, including per-core voltage regulation loops through Fully Integrated Voltage Regulators. Based on a nonlinear descriptor formulation of the system equations, we propose a transient solver based on a two-level Waveform Relaxation iteration. The convergence properties and the scalability of this solver when implemented on a parallel computing architecture are investigated. Numerical results show fast convergence and excellent scalability properties
Fast Transient Simulation of System-Level Power Delivery Networks via Parallel Waveform Relaxation
Full text linkThis application paper addresses the problem of transient simulation of system-level Power Distribution Networks (PDN) of multicore processing systems. In particular, we consider a post-layout Power Integrity verification problem where all system parts are finalized and a highly accurate transient verification is performed to ensure that voltage supply signals remain within prescribed bounds when the PDN is loaded by realistic current stimuli. Systems with tens of even hundreds of cores are considered, equipped with per-core local voltage stabilization, attained through Integrated Voltage Regulators (IVR) suitably controlled by sensing and feedback loops. Transient simulation of such system-level PDNs becomes particularly challenging when interconnect models or macromodels computed by electromagnetic solvers are embedded. In order to break system complexity, we propose a set of algorithms based on an ad-hoc system partitioning strategy, combined with multi-level Waveform Relaxation (WR) schemes. The main advantage of this approach is a straightforward parallelization, aimed at solving concurrently by parallel computing threads only small and well-defined circuit partitions. Several partitioning and associated WR schemes are discussed and tested, showing excellent scalability with up to 60 computing threads, with significant speedup in runtime with respect to a standard SPICE-based approach
A Compressed Multivariate Macromodeling Framework for Fast Transient Verification of System-Level Power Delivery Networks
Full text linkThis paper discusses a reduced-order modeling and simulation approach for fast transient power integrity verifi- cation at full system level. The reference structure is a com- plete power distribution network (PDN) from platform voltage regulator module (VRM) to multiple cores, including board, package, decoupling capacitors, and per-core fully integrated voltage regulators (FIVR). All blocks are characterized and known through high-fidelity models derived from first-principle solvers (full-wave electromagnetic and circuit-level extractions). The complexity of such detailed characterization grows very large and becomes intractable, especially for power integrity verification of massive multicore platforms subjected to real workload scenarios. We approach this problem by exploiting a multi-stage macromodeling and compression process, leading to a compact representation of the system dynamics in terms of a linearized state-space structure with multiple feedback loops from the FIVR controllers. The PDN macromodel is obtained through a data-driven approach starting from reference small- signal frequency responses, obtaining a sparse and structured representation specifically designed to match the behavior of the reference system. The resulting compact model is then solved in time-domain very efficiently. Results on mobile and enterprise server benchmarks demonstrate a speedup in runtime up to 50× with respect to HSPICE, with negligible loss of accuracy
Analysis of Dielectric Waveguides and Microstrip Lines Using Krylov Subspace-Based Techniques
No full text132 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2000.In this thesis, we have developed a finite-difference-based frequency domain scheme to analyze a wide variety of waveguides and microstrip lines. The formulation is generalized to account for anisotropic, lossy substrates. In order to speed up the algorithm, the discretization is limited to the two-dimensional transverse plane while propagating the wave analytically along the longitudinal direction. The performance of the algorithm is further improved by using Krylov subspace-based reduction techniques to solve the sparse matrix equation. The numerical technique is also extended to analyze single and multiple discontinuities in the waveguiding structure. Finally, some preliminary work is done on truncation of the computational domain using perfectly matched layers (PML) as a material absorbing boundary conditions.U of I OnlyRestricted to the U of I community idenfinitely during batch ingest of legacy ETD
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