5,230 research outputs found
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions
No full textA novel reconfigurable switched-capacitor "EChO" Power Management Unit is introduced for ultra-low power duty-cycled integrated systems (e.g., sensor nodes for critical event monitoring). "EChO" reduces the energy cost associated with sleep-to-active and active-to sleep transitions by 64% with an area overhead less than 1% and no impact on active mode operation. Analysis shows that approximately the same energy reduction is achieved over a very wide range of operating conditions and design constraints (e.g., ratio between flying and decoupling capacitances, granularity of the capacitor array). Measurements show 25-30% system power saving for a 65-nm testchip implementation of the "EChO" PMU powering a 16-kgate processing unit and a 2-kbit SRAM at 0.55-V voltage in active mode, assuming a 1-s wakeup cycle, 6.25-12.5% activity and a processing task of 250 cycles. The technique can be synergistically employed with traditional reconfiguration techniques that focus on efficiency in active mode (ignoring active-sleep transitions) to sum up the benefits. © 1966-2012 IEEE
Design Methodology and Tools for Wireless System Design Jan M. Rabaey
No full textThe remarkable breakthrough that wireless systems have experienced in the last decade seems to be only the first wave of a wireless revolution that will have a profound effect on industries such as communications, computing, and consumer. The underlying premise is that wireless will be the preferred way of connecting various electronic devices and systems. Designing the optimized radio modules that support the range of applications, services, and bandwidths while staying cost-effective proves to be a major challenge and requires an integrated design flow augmented with the appropriate tools. This presentation will forward a vision on how such a flow could be constructed
Efficient Biosignal Processing Using Hyperdimensional Computing: Network Templates for Combined Learning and Classification of ExG Signals
Get PDFRecognizing the very size of the brain's circuits, hyperdimensional (HD) computing can model neural activity patterns with points in a HD space, that is, with HD vectors. Key examined properties of HD computing include: a versatile set of arithmetic operations on HD vectors, generality, scalability, analyzability, one-shot learning, and energy efficiency. These make it a prime candidate for efficient biosignal processing where signals are noisy and nonstationary, training data sets are not huge, individual variability is significant, and energy-efficiency constraints are tight. Purely based on native HD computing operators, we describe a combined method for multiclass learning and classification of various ExG biosignals such as electromyography (EMG), electroencephalography (EEG), and electrocorticography (ECoG). We develop a full set of HD network templates that comprehensively encode body potentials and brain neural activity recorded from different electrodes into a single HD vector without requiring domain expert knowledge or ad hoc electrode selection process. Such encoded HD vector is processed as a single unit for fast one-shot learning, and robust classification. It can be interpreted to identify the most useful features as well. Compared to state-of-the-art counterparts, HD computing enables online, incremental, and fast learning as it demands less than a third as much training data as well as less preprocessing
Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches
No full textIn this paper, a new class of pulsed latches is introduced and experimentally assessed in 65-nm CMOS. Its conditional push-pull pulsed latch topology is based on a push-pull final stage driven by two split paths with a conditional pulse generator. Two circuit implementations of the concept are discussed, with their main difference being in the pulse generator, which can be either shared ((CSPL)-L-3) or not ((CPL)-L-3). Measurements show that the proposed topology is very fast, as it outperforms the well-known transmission gate pulsed latch (TGPL) [1] by 1.5x-2x; hence the proposed pulsed latch has the highest performance ever reported. The proposed pulsed latch is also shown to significantly improve the energy efficiency compared to the state of the art. Indeed, a 2.3x improvement in ED3 product (energy x delay(3)) over TGPL was found for designs targeting minimum ED3. For designs targeting minimum ED, a 1.3x improvement was found in ED product. This comes at the cost of a 1.15x-1.35x cell area penalty, which translates into an overall area increase well below 1% in typical systems. Measurements on 256 replicas confirm that the above benefits are kept in the presence of variations. Accordingly, the proposed class of pulsed latches goes beyond the current state of the art and is well suited for VLSI systems that require both high performance and energy efficiency
Design and characterization of a 65nm CMOS wireless RFID reader for ECoG tag
No full textA 5uV-resolution RFID ECoG data reader has been
designed and implemented in 65nm CMOS TSMC technology. The
area occupancy is 1.8mmxl.9mm. In this paper, the design and
measurement results are shown. The circuit average power
consumption is less than 36pW for the analog part while the peak
power ofthe digital one is 19mW (including the output butTers and
protections) with supply of 1.2V, providing power transmission
300MHz by a class EPA. The data coming from IMHz from the
tag modulates the AC power and the envelope detector allow the
acquisition. The asynchronous demodulation achieves a HER less
than 10-6. The novelty of the solution and the experimental
measurements propose the architecture as a pioneer for the ECoG
reading out architecture
Digital integrated circuits: a design perpectives/ Rabaey
No full textxviii, 702 hal.; ill.tab.; 24 cm
Digital Integrated CircuitsA Design Perspective
No full textPresent intuitive understanding of device operation
Introduction of basic device equations
Introduction of models for manual analysis
Introduction of models for SPICE simulation
Analysis of secondary and deep-sub-micron effects
Future trend
Hyperdimensional biosignal processing: A case study for EMG-based hand gesture recognition
No full textThe mathematical properties of high-dimensional spaces seem remarkably suited for describing behaviors produces by brains. Brain-inspired hyperdimensional computing (HDC) explores the emulation of cognition by computing with hypervectors as an alternative to computing with numbers. Hypervectors are high-dimensional, holographic, and (pseudo)random with independent and identically distributed (i.i.d.) components. These features provide an opportunity for energy-efficient computing applied to cyberbiological and cybernetic systems. We describe the use of HDC in a smart prosthetic application, namely hand gesture recognition from a stream of Electromyography (EMG) signals. Our algorithm encodes a stream of analog EMG signals that are simultaneously generated from four channels to a single hypervector. The proposed encoding effectively captures spatial and temporal relations across and within the channels to represent a gesture. This HDC encoder achieves a high level of classification accuracy (97.8%) with only 1/3 the training data required by state-of-the-art SVM on the same task. HDC exhibits fast and accurate learning explicitly allowing online and continuous learning. We further enhance the encoder to adaptively mitigate the effect of gesture-timing uncertainties across different subjects endogenously; further, the encoder inherently maintains the same accuracy when there is up to 30% overlapping between two consecutive gestures in a classification window
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