1,721,059 research outputs found
End-to-End Planner for Self-Reconfigurable Modular Robots Collaborative Objects Manipulation, Transport and Handover to Human Application
No full textThis work was funded in part by IMEC and the EPFL Center for Intelligent Systems (CIS)
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions
No full textA novel reconfigurable switched-capacitor "EChO" Power Management Unit is introduced for ultra-low power duty-cycled integrated systems (e.g., sensor nodes for critical event monitoring). "EChO" reduces the energy cost associated with sleep-to-active and active-to sleep transitions by 64% with an area overhead less than 1% and no impact on active mode operation. Analysis shows that approximately the same energy reduction is achieved over a very wide range of operating conditions and design constraints (e.g., ratio between flying and decoupling capacitances, granularity of the capacitor array). Measurements show 25-30% system power saving for a 65-nm testchip implementation of the "EChO" PMU powering a 16-kgate processing unit and a 2-kbit SRAM at 0.55-V voltage in active mode, assuming a 1-s wakeup cycle, 6.25-12.5% activity and a processing task of 250 cycles. The technique can be synergistically employed with traditional reconfiguration techniques that focus on efficiency in active mode (ignoring active-sleep transitions) to sum up the benefits. © 1966-2012 IEEE
Ultralow-power radio frequency beamformer using transmission-line transformers and tunable passives
No full textNovel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches
No full textIn this paper, a new class of pulsed latches is introduced and experimentally assessed in 65-nm CMOS. Its conditional push-pull pulsed latch topology is based on a push-pull final stage driven by two split paths with a conditional pulse generator. Two circuit implementations of the concept are discussed, with their main difference being in the pulse generator, which can be either shared ((CSPL)-L-3) or not ((CPL)-L-3). Measurements show that the proposed topology is very fast, as it outperforms the well-known transmission gate pulsed latch (TGPL) [1] by 1.5x-2x; hence the proposed pulsed latch has the highest performance ever reported. The proposed pulsed latch is also shown to significantly improve the energy efficiency compared to the state of the art. Indeed, a 2.3x improvement in ED3 product (energy x delay(3)) over TGPL was found for designs targeting minimum ED3. For designs targeting minimum ED, a 1.3x improvement was found in ED product. This comes at the cost of a 1.15x-1.35x cell area penalty, which translates into an overall area increase well below 1% in typical systems. Measurements on 256 replicas confirm that the above benefits are kept in the presence of variations. Accordingly, the proposed class of pulsed latches goes beyond the current state of the art and is well suited for VLSI systems that require both high performance and energy efficiency
Automatic 3D Design for Efficiency Optimization of a Class E Power Amplifier
No full textA design tool, which exploits a State Space model description for the automatic design of a Class-E Power Amplifier, is here proposed. The tool provides an automatic optimization of the filter components, just by inserting the design specifications and the starting values. The second step of the automatic iterative tuning allows preserving the highest value of power efficiency. All specifications realize a 3D matrix, which is able to converge (with 60 iterations in about 3s) to an optimal solution by using the crosscheck of the specifications. Finally, as case study, a η-optimal design has been implemented by using the proposed tool. We compare the analytical design of the Class E PA implemented in TSMC 65nm CMOS technology, with the State Space Model technique here described. The new design reaches an efficiency of 87% in simulation, with an η increment of 12% respect the original design
Digital Integrated CircuitsA Design Perspective
No full textPresent intuitive understanding of device operation
Introduction of basic device equations
Introduction of models for manual analysis
Introduction of models for SPICE simulation
Analysis of secondary and deep-sub-micron effects
Future trend
Design and characterization of a 65nm CMOS wireless RFID reader for ECoG tag
No full textA 5uV-resolution RFID ECoG data reader has been
designed and implemented in 65nm CMOS TSMC technology. The
area occupancy is 1.8mmxl.9mm. In this paper, the design and
measurement results are shown. The circuit average power
consumption is less than 36pW for the analog part while the peak
power ofthe digital one is 19mW (including the output butTers and
protections) with supply of 1.2V, providing power transmission
300MHz by a class EPA. The data coming from IMHz from the
tag modulates the AC power and the envelope detector allow the
acquisition. The asynchronous demodulation achieves a HER less
than 10-6. The novelty of the solution and the experimental
measurements propose the architecture as a pioneer for the ECoG
reading out architecture
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