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From GaAs to GaN technology: study of limits and reliability of High Electron Mobility Transistors
Full text linkHigh Electron Mobility Transistors (HEMTs) are finding wide applications in many areas, including microwave power amplifiers, radars, communication and conversion fields. The high mobility, due to the reduction of scattering phenomena, and the high carrier density, due to the confinement of electrons in the so called 2DEG, allowed the achievement of a high current density and low channel resistance, thus making these devices very suitable for high frequency applications.
HEMTs are usually based on III-V materials, especially GaAs and GaN technology, as a consequence of their electrical properties. In the last years gallium nitride has become one of the most interesting and suitable material. The high direct energy gap led to better performances especially in optoelectronic devices such as Light emitting diodes, lasers and detectors. Furthermore, the high carrier saturation velocity and the high mobility demonstrated high performances in devices aimed at high frequency, such as HEMTs. Finally the high electric field breakdown and Johnson’s figure of merit suggest its use for devices with high power requirements, thus overcoming in many areas gallium arsenide technology. For many applications, such as MMIC (monolithic microwave integrated circuits) structures, gallium arsenide is preferable, mainly as a consequence of excellent charge transport properties and low loss at microwave and millimetre-wave frequencies. Furthermore, especially for commercial purposes, gallium arsenide is more used due to the well-established technology.
Although the significant intrinsic properties, both gallium arsenide and gallium nitride HEMT technology are still affected by reliability issues which limit their performances in common applications. The purpose of this thesis is to study reliability topics which limit HEMT technology on the basis of materials used, namely GaAs, GaN, InAlN, in order to define corresponding limits and performances. With the aim of providing for a more complete perspective the analysis will focus not only on discrete transistors but it will be extended also on complete structures such as power amplifiers.
Within this work we present a detailed study of two main degradation mechanisms which still affect GaAs technology and limit its performances both in discrete pHEMTs and in commercial complete structures: thermal degradation and electrostatic discharge failure. Thermal degradation analysis has been firstly studied on discrete structures, namely pseudomorphic HEMTs. A first purpose is to define main failure mechanisms and modes by means of a long term thermal stress with no bias applied. Several analysis (DC, pulsed, end resistances and barrier height evaluation) has been proposed to monitor devices behaviour. Degradation appears to be non-monotonic, i.e. drain current first decreases, then increases again, following the corresponding shifts in the threshold voltage. Although the initial decrease of drain current could be attributed to gate metal interdiffusion, or "gate sinking", leading to a positive shift of threshold voltage, it is accompanied by a variation of the maximum value of transconductance and an increase of end resistances, that suggest a concurrent degradation of ohmic contacts. A third mechanism, represented by the Schottky barrier height, counteracts the effect of gate interdiffusion and eventually prevails, leading to an opposite shift of the threshold voltage.
Devices used for high power applications can reach high junction temperatures as a consequence of the power dissipation, demonstrating the importance of accurately defining the thermal resistance, i.e. the channel temperature variation as a function of power dissipated. A second purpose of this chapter is to provide for a detailed description of different techniques (namely DC, pulsed and infrared thermal camera) to estimate channel temperature of HEMTs and to present a critical comparison among them. Differently from DC and pulsed evaluation, analysis with IR thermal camera strongly underestimates the results. With the aim of understanding the impact of inaccuracies on a high frequency application the analysis has been extended to a four stage MMIC power amplifier. The strong underestimation of IR method has been confirmed; furthermore the thermal interaction among different stages and its impact on the structure has been studied. By means of a deep analysis of thermal resistance a HTOL test has been proposed on power amplifiers, submitting the devices both to an electrical and thermal stress and confirming that no significant effect is noticed if a junction temperature lower or equal to 250°C is reached. Comparison between VTH shift in HTOL and thermal stress suggests that the junction temperature has been slightly underestimated.
Electrostatic discharge robustness has been studied on a four stage MMIC power amplifier based on GaAs pHEMT technology used in commercial point to point microwave systems. The structure is characterized by a ESD protection circuit mainly defined by Schottky diodes protection structures at the gate terminals and resonant circuit protection structure at the RF input and output pads. Robustness has been analysed with a 100ns TDR-TLP. Results have been confirmed with HBM and MM tests. No failures are observed in the RF-IN, RF-OUT and Drain connections vs. GND up to ±2 kV and ±200 V HBM and MM respectively. RF pads failed with TLP analysis at about 6.5-7A, resulting in an open circuit at the inductor and a short at the capacitor of the resonant structure. Gate connections fail in correspondence of the negative HBM pre-charge value starting from -1.0 kV; MM stresses lead to the failure of the Gate connections from -50 V. Failures are due to the damage of anti-parallel Schottky diodes acting as ESD protection structures. The auxiliary connections reveal to be the most sensitive I/Os of the entire PA, failing at 250 V and 25 V, respectively HBM and MM, due to the failure of integrated resistors.
A second part of the thesis mainly focuses on AlGaN/GaN devices. One of the main aspects which limit devices RF and power performances is the so-called current collapse and trapping effects. Therefore a detailed analysis has been proposed on devices characterized by a different iron doping in the buffer layer aimed at preventing parasitic effects and punch through phenomenon. The aim is to define a correlation between the trapping behaviour and iron doping in the buffer layer. A further purpose is to study the correlation between several degradation phenomena when a reliability stress is imposed, both in terms of DC characterization, trapping effects and light emission analysis. A comparison of the correlation between different degradation phenomena in devices with several iron doping quantities is finally proposed. Results are consistent with further investigations reported in literature which correlate the use of iron doping to a trap level with activation energy of 0.57-0.7eV.
The analysis firstly demonstrates that iron doping determines a measurable current collapse, which is related to the presence of a trap (T1) located in the buffer with time constant of 3.2ms at T=40°C. Trapping location is consistent with the amplitude significant increase with Fe-concentration in the buffer. Furthermore trap T1 reveals a lower activation energy in devices with no iron doping. The amplitude of trap T1 in devices with different structures and comparison with works reported in literature suggest that the trap is due to an intrinsic defect in the buffer layer characteristic of GaN, although its concentration strongly depends on buffer doping quantity. Results of current transients with different filling pulses applied suggest that trapping is due to line defects or point defects clustering around dislocations. A second trap, T2, is detected. According to comparison of devices with different iron doping and comparison with gm(f) analysis we can suppose that T2, characterized by a time constant of 0.25s at T=40°C, is probably located in the AlGaN layer.
Results of an electrical stress applied to the gate terminal of Fe doped devices indicate that the main consequences of the stress experiments are (i) an increase in the leakage gate current, which is strongly correlated to light emission and – beyond the critical voltage – to an increase in the current collapse and (ii) the increase in the transient signal associated with the pre-existing trap levels, without the generation of new traps. Discussion about different results related to the Fe doping buffer layer demonstrates that, when submitted to step-stress, all the devices show a significant and permanent increase in gate leakage current. Furthermore stress induces also an increase in current collapse, which is not correlated to the generation of new trap levels but originates from the increase in the signal associated with the pre-existing trap levels T1 and T2. The change in the signal of T2 (which is supposed to be located in the AlGaN barrier) may be due to an increase in the concentration of a defect (T2); the change of T1, (probably located in the buffer layer) can be explained by the generation of defect-related conductive paths between the gate and the channel which enhance transfer electrons toward the trap states.
In the last part new materials to improve GaN technology performances are studied. InAlN/GaN structures are becoming very important as a consequence of the higher carrier density in the 2DEG and the possible achievement of a lattice matched structure, thus significantly improving device electrical and thermal stability. Further improvements, especially at the contacts, will be presented within this thesis. A first analysis consists of the use of a different material for the Schottky gate contact. A comparison of InAlN/GaN HEMTs with analogous structure but different gate, namely Mo/Au and Ni/Pt/Au, is studied. Despite no significant variation is noticed during DC analysis, pulsed evaluation demonstrates that the use of a Mo/Au gate contact leads to an improvement of trapping characteristics, mainly due to the process used for contact deposition. By means of a three terminals step stress it is finally proved that Mo/Au does not significantly affect device stability.
A second analysis consists of the definition of a recess before the deposition of ohmic contacts to reduce parasitic resistances. The comparison is proposed for two different wafer, characterized by a similar but not analogous structure and different Carbon doping quantity to avoid parasitic leakage current. DC analysis shows that a significant variation is noticed in IDSS value, showing that a lower value corresponds to structures with recess at the ohmic contacts. This aspect is mainly due to the fact that a lower on resistance measured in linear zone is not obtained. Pulsed analysis states a high current collapse value with no significant correlation with device structure or presence of recess at the ohmic contacts. Drain current transient reveals two main traps, labelled T1 and T2. Activation energy, differently from the cross section value, is not influenced by device structure or by recess at the ohmic contacs. On the basis of drain current transients, gm(f) analysis and previous works reported in literature we can speculate that trap T2 is located in the buffer layer, differently from trap T1 which is probably in the AlGaN layer. Filling time measurements indicate that both the traps are mainly due to line defects
Reverse-bias stress of high electron mobility transistors: Correlation between leakage current, current collapse and trap characteristics
No full textThis paper describes an investigation of the effect of reverse-bias stress on the leakage current and trapping characteristics of GaN based HEMT. The analysis is based on combined electrical, transient and electroluminescence measurements, carried out during the execution of step-stress experiments. The experimental data collected within this work indicate that: (i) when submitted to reverse bias stress, beyond a certain critical voltage, the devices can show a significant increase in leakage current, which is correlated to the generation of luminescence spots, that can be identified by means of EL measurements; (ii) beyond the critical voltage, the increase in gate leakage is correlated to an increase in current collapse; (iii) transient measurements, carried out to get information on the origin of current collapse, identify the existence of two trap levels (T1 and T2). Results suggest that stress does not induce the generation of new defective levels, but only the increase in the amplitude of the current transients associated to pre-existing traps. © 2013 Elsevier Ltd. All rights reserved
A novel high voltage and high speed measurement system for dynamic RON measurements in GaN‐based high mobility transistors (HEMTs)
No full text
Indirect techniques for channel temperature estimation of HEMT microwave transistors: Comparison and limits
No full textThis paper presents a critical comparison of three different methods for the estimation of the thermal
resistance (RTH) of GaAs pHEMTs: (i) a DC method, based on the use of drain current as a temperature
sensitive parameter (TSP); (ii) a pulsed I–V method, based on the evaluation of IDS at different temperature
levels, (iii) infrared thermography.
DC and pulsed measurements were carried out on several multifinger GaAs pHEMTs characterized by
different gate width values. Results provide information on the dependence of the thermal characteristics
of the HEMTs on the main device parameters, and on the differences between the methods adopted for
RTH extrapolation. Moreover, DC analysis and infrared thermography was extended to complete MMIC
structures: experimental results provide information on the cross-thermal resistance existing between
the different components of the analyzed circuits, as a function of the operating conditions of each stage
Trapping phenomena in AlGaN/GaN HEMTs: A study based on pulsed and transient measurements
No full textSlow trapping phenomenon in AlGaN/GaN HEMTs has been extensively analyzed and described in this paper. Thanks to a detailed investigation, based on a combined pulsed and transient investigation of the current/voltage characteristics (carried out over on an 8-decade time scale), we report a detailed description of the properties of trap levels located in the gate-drain surface, and in the region under the gate of AlGaN/GaN HEMTs. More specifically, the following, relevant results have been identified: (i) the presence of surface trap states may determine a significant current collapse, and reduction of the peak transconductance. During a current transient measurement, the emission of electrons trapped at surface states proceeds through hopping, as demonstrated by means of temperature-dependent measurements. The activation energy of the de-trapping process is equal to 99 meV. (ii) The presence of a high density of defects under the gate may induce a significant shift in the threshold voltage, when devices are submitted to pulsed transconductance measurements. The traps responsible for this process have an activation energy of 0.63 eV, and are detected only on samples with high gate leakage, since gate current allows for a more effective charging/de-charging of the defects. © 2013 IOP Publishing Ltd
Extensive Investigation of Time-Dependent Breakdown of GaN-HEMTs Submitted to OFF-State Stress
No full textThis paper reports the experimental demonstration of time-dependent dielectric breakdown in GaN-based high-electron mobility transistors (HEMTs) submitted to OFF-state stress. Based on combined breakdown measurements, constant voltage stress tests, and 2-D simulations, we demonstrate the following relevant results. First, GaN-based HEMTs with a breakdown voltage higher than 1000 V (evaluated by dc measurements) may show time-dependent failure when exposed to OFF-state stress with VDS in the range 600-700 V. Second, time-to-failure (TTF) is Weibull-distributed, and has an exponential dependence on the stress voltage level. Third, time-dependent breakdown is ascribed to the failure of the SiN dielectric at the edge of the gate overhang, on the drain side. Fourth, 2-D simulations confirm that-in this region-the electric field exceeds 6 MV/cm, i.e., the dielectric strength of SiN. Finally, we demonstrate that by limiting the electric field in the nitride through epitaxy and process improvements, it is possible to increase the TTF by three orders of magnitude. © 1963-2012 IEEE
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