1,721,339 research outputs found
70-MHz 2-μm CMOS Bit-level Systolic Arrat Median Filter
No full textA novel algorithm for VLSI median filtering of one-dimensional signals of complexity linearly dependent on the filter window length is described in this paper. The algorithm is implemented as a bit-level systolic array (BLSA), in order to achieve a high performance. A single-chip median filter characterized by a window length of 25 8-b samples, and by the operation on three interleaved independent sequences for a total of 75 samples, is also presented as a demonstrator. The throughput relevant to one sequence is 1/3 in this chip, whereas the theoretical maximum allowed by the algorithm is 1/2. Prototypes designed with a 2-mum CMOS technology have been successfully tested at a clock frequency over 70 MHz
Efficient Sine Evaluation Architecture for Direct Digital Frequency Synthesis
No full textAn efficient sine evaluation architecture for direct digital frequency synthesis (DDFS) is presented. The sine values are approximated with the output of a second order interpolator, whose coefficients are stored in a tiny look-up table (LUT). The method allows a strong memory compression ratio, with respect to other approximation solutions, that balances the necessity of two multipliers and two adders. A sine evaluator with 21-b argument and 16-b output has been designed. It is characterized by a maximum absolute error of 0.82 LSB, an output SNR of 97.78 dB and an amplitude contribution to the spectral purity better than 117 dBc. The dimension of the LUT is only 720 b, and the parabolic interpolator has an estimated complexity of about 15,000 transistors. The structure of the evaluator is simple, easily pipelinable, and well suited to an integrated implementation
A Single Chip Adaptive Filter for Delta-Modulated Signals
No full textIn this paper the VLSI design of a single chip programmable transversal filter for Delta-Modulated signals is presented.
In particular, it is shown how the relatively complex function of such a filter is realized with sistolic structures of high regularity and with a high degree of parallelism.
With reference to the CMOS technology, really used for the chip, a more detailed description of the main blocks is therefore given.
Timing performances of the whole chip are analyzed: the lack of broadcasting allows the chip to work at a frequency near the limits of the used devices
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