1,720,977 research outputs found
Towards Compelling Cases for the Viability of Silicon-Nanophotonic Technology in Future Many-core Systems
Full text linkMany crossbenchmarking results reported in the open literature raise optimistic expectations on the use of optical networks-on-chip (ONoCs) for high-performance and low-power on-chip communications in future Manycore Systems. However, these works ultimately fail to make a compelling case for the viability of silicon-nanophotonic technology for two fundamental reasons:
(1)Lack of aggressive electrical baselines (ENoCs).
(2) Inaccuracy in physical- and architecture-layer analysis of the ONoC.
This thesis aims at providing the guidelines and minimum requirements so that nanophotonic emerging technology may become of practical relevance. The key enabler for this study is a cross-layer design methodology of the optical transport medium, ranging from the consideration of the predictability gap between ONoC logic schemes and their physical implementations, up to architecture-level design issues such as the network interface and its co-design requirements with the memory hierarchy. In order to increase the practical relevance of the study, we consider a consolidated electrical NoC counterpart with an optimized architecture from a performance and power viewpoint. The quality metrics of this latter are derived from synthesis and place&route on an industrial 40nm low-power technology library. Building on this methodology, we are able to provide a realistic energy efficiency comparison between ONoC and ENoC both at the level of the system interconnect and of the system as a whole, pointing out the sensitivity of the results to the maturity of the underlying silicon nanophotonic technology, and at the same time paving the way towards compelling cases for the viability of such technology in next generation many-cores systems
Design Space Exploration of Wavelength-Routed Optical NoC Topologies for 3D-Stacked Multi- and Many-Core Processors.
No full text1) Introduction
2) Silicon Photonics as a Technology Enabler
2a) Optical Links
2b) Modulators
2c) Photonic-Switching Elements and Optical Routers for Optical Networks-on-Chip
2d) Photodetectors
2e) Laser Sources
3) Need for Pathfinding
4) Predictability-Critical ONoC Topologies
5) Design Space Exploration of Wavelength-Routed Topologies
5a) Global Connectivity
5b) Network Partitioning
5c) Comparison with an Optical Ring Topology
5d) Network Partitioning
5f) Logic Topologies
5e) Physical Topologies
5g) Power Efficiency of Topologies
5h) Global Connectivity vs. Network partitioning
6) Spatial-Division-Multiplexing Ring Topology vs. Filter-based Topology
7) Conclusion
8) Reference
Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints
No full textThe performance of future chip multi-processors will only scale with the number of integrated cores if there is a corresponding increase in memory access efficiency. The focus of this paper on a 3D-stacked wavelength-routed optical layer for high bandwidth and low latency processor-memory communication goes in this direction and complements ongoing efforts on photonically integrated bandwidth-rich DRAM devices. This target environment dictates layout constraints that make the difference in discriminating between alternative design choices of the optical layer. This paper assesses network partitioning options and bandwidth scalability techniques with deep technology and layout awareness, the main contribution lying in the characterization and precise quantification of such interaction effects between the technology platform, the layout constraints and the network-level quality metrics of a passive optical NoC
Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors
No full textThere is still a significant gap between the optical network-on-chip (NoC) concept and a mature interconnect technology with practical relevance. Current research aims at bridging this gap by evolving basic optical components and by developing ad-hoc design tools to enable their use for system-level design. This paper points out another cause for the design predictability gap of optical NoC topologies, namely the physical placement of network interfaces in the target floorplan. Building on this awareness, the paper compares power efficiency of the most relevant topologies proposed so far for wavelength-routed optical NoCs in the context of a 3D-stacked multi-core processor
The Design Predictability Concern in Optical Network-on-Chip Design
No full textPredictability is a well-known concern for electronic circuit design. This paper shows that it is a concern for optical network-on-chip design too. The gap between logic and physical topologies is used as a case study. © OSA 2012
PROTON+: A placement and routing tool for 3d optical networks-on-chip with a single optical layer
No full textOptical Networks-on-Chip (ONoCs) are a promising technology to overcome the bottleneck of low bandwidth of electronic Networks-on-Chip. Recent research discusses power and performance benefits of ONoCs based on their system-level design, while layout effects are typically overlooked. As a consequence, laser power requirements are inaccurately computed from the logic scheme but do not consider the layout. In this article, we propose PROTON+, a fast tool for placement and routing of 3D ONoCs minimizing the total laser power. Using our tool, the required laser power of the system can be decreased by up to 94% compared to a state-ofthe- art manually designed layout. In addition, with the help of our tool, we study the physical design space of ONoC topologies. For this purpose, topology synthesis methods (e.g., global connectivity and network partitioning) as well as different objective function weights are analyzed in order to minimize the maximum insertion loss and ultimately the system's laser power consumption. For the first time, we study optimal positions of memory controllers. A comparison of our algorithm to a state-of-The-Art placer for electronic circuits shows the need for a different set of tools custom-Tailored for the particular requirements of optical interconnects
Integrated Cross-Layer Solutions for Enabling Silicon Photonics into Future Chip Multiprocessors
No full textNanophotonic is a promising solution for interconnections in future chip multiprocessors (CMPs) due to its intrinsic low-latency and low-power features. This paper proposes an integrated approach with physical level design choices to select the most suitable optical network topology, and an adhoc software strategy to improve performance and reduce energy consumption of a tiled CMP architecture. We adopt an all-optical reconfigurable network which has been designed to significantly reduce path-setup latency and energy consumption. Specifically the optimization aims at distributing the traffic into the Network on Chip (NoC) in such a way to limit resurce usage conflicts (during path-setups) and have a more uniform utilization of the fast optical resources. On-chip photonics indeed is the key enabler for such a strategy permitting to reach even far destinations with a reduced latency, the same as the closest ones. We investigate performance/power consumption effects on a CMP system and we compare against both a high-performance electronic folded Torus NoC and the standard optical reconfigurable architecture. The optical network improves 7% on average over the electronic counterpart and, especially when using the dedicated software optimization for matching application locality and network features, it reaches about 26% average execution time improvement
Capturing the sensitivity of optical network quality metrics to its network interface parameters
No full textOptical networks-on-chip (ONoCs) are gaining momentum as a way to improve energy consumption and bandwidth scalability in the next generation multicore and many-core systems. Although many valuable research works have investigated their properties, the vast majority of them lack an accurate exploration of the network interface architecture required to support optical communications on the silicon chip. The complexity of this architecture is especially critical for a specific kind of ONoCs: the wavelength-routed ones. These are capable of delivering contention-free all-to-all connectivity without the need for path reservation, unlike space-routed ONoCs. From a logical viewpoint, they can be considered as full nonblocking crossbars; thus, the control complexity is implemented at the network interfaces. To our knowledge, this paper proposes the first complete network interface architecture for wavelength-routed optical NoCs, by coping with the intricacy of networking issues such as flow control, buffering strategy, deadlock avoidance, serialization, and above all, their codesign in a complete architecture. The evaluation methodology spans from area and energy analysis via actual synthesis runs in 40-nm technology to RTL-equivalent (register-transfer level) SystemC modelling of the network architecture and aims at verifying whether the projected benefits of ONoCs versus their electrical counterparts are still preserved when the complexity of their network interface is considered in the analysi
Exploring Communication Protocols for Optical Networks-on-Chip based on Ring Topologies
No full textPrevious studies report on the promising features of ring structures to serve as the interconnection backbone for optical networks-on-chip. This paper contrasts the power efficiency of Wavelength-Selective vs. Arbitrated Routing Methods with technology and layout awareness
Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems
No full textThe fundamental choice to be taken when sharing an optical ring between multiple communication actors is whether to avoid contention from the ground up by means of non-interfering concurrent transmissions on different wavelengths, or by resolving it at runtime through arbitration mechanisms.This paper aims at assessing power efficiency of Wavelength-Selective vs. Wavelength-Arbitrated routing methodologies on top of an optical ringfor photonically-integrated high-end embedded systems
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