164 research outputs found
A Constant-Energy-Packet-Extraction-Based MPPT Technique With 98% Average Extraction Efficiency for Wide Range Generic Ambient Energy Scavenging Supporting 1000 × Source Resistance Range
No full textAn energy harvesting system, featuring a novel generic maximum power point (MPP) tracking technique, compatible with a wide range of transducers is presented in this work. In conventional harvesting systems, the MPP tracking requires frequent open circuiting or prior knowledge about the transducer parameters. The proposed constant-energy-packet-extraction (CEPE) technique uses the technique of increasing the rate of energy extraction by frequency modulation to reach MPP and hence eliminates the need to open circuit, as well as the need for prior knowledge about the transducer parameters. The prototype system achieves an average extraction efficiency of 98% for a wide input voltage range from 50 to 500 mV and transducers with internal impedance ranging from 3 to 3.5 k. The converter has a peak end-to-end efficiency of 81.8%. A shared inductor-based startup technique is also integrated with the system, which can start operation from a minimum input voltage of 150 mV with minimal external components. It reuses the boost converter inductor, and hence, the system requires only one inductor and three capacitors as external components. The prototype chip is fabricated in 180-nm CMOS technology and occupies an on-chip area of 1.65 mm , including startup. IEE
Applying empirical thresholding algorithm for a keystroke dynamics based authentication system
No full textEntrepreneurial marketing in subsistence marketplaces
No full textThere are more than a billion poverty-stricken entrepreneurs in the world who run micro-enterprises to meet basic consumption needs. This pervasive phenomenon presents an interesting theoretical conundrum - that of consumer-entrepreneur duality. This duality blurs the boundaries between consumption and entrepreneurship, which have traditionally been distinct domains of scholarly inquiry. The research reported in this dissertation aims to a) provide a theoretical foundation for the notion of consumer-entrepreneur duality and b) test the implications of the aforementioned duality empirically. A key insight flowing from the investigations is that factors in the consumption domain impact important outcomes in the entrepreneurial domain and vice versa.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2018-05-01The student, Srinivas Venugopal, accepted the attached license on 2016-04-18 at 08:47.The student, Srinivas Venugopal, submitted this Dissertation for approval on 2016-04-18 at 09:04.This Dissertation was approved for publication on 2016-04-19 at 08:14.DSpace SAF Submission Ingestion Package generated from Vireo submission #9286 on 2016-07-07 at 14:17:05Made available in DSpace on 2016-07-07T21:17:37Z (GMT). No. of bitstreams: 4
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Previous issue date: 2016-04-19Embargo set by: Seth Robbins for item 93274
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Aggregate breakdown of nanoparticulate titania
No full textSix nanosized titanium dioxide powders synthesized from a sulfate process were investigated. The targeted end-use of this powder was for a de-NOx catalyst honeycomb monolith. Alteration of synthesis parameters had resulted principally in differences in soluble ion level and specific surface area of the powders. The goal of this investigation was to understand the role of synthesis parameters in the aggregation behavior of these powders. Investigation via scanning electron microscopy of the powders revealed three different aggregation iterations at specific length scales.
Secondary and higher order aggregate strength was investigated via oscillatory stress rheometry as a means of simulating shear conditions encountered during extrusion. G' and G'' were measured as a function of the applied oscillatory stress. Oscillatory rheometry indicated a strong variation as a function of the sulfate level of the particles in the viscoelastic yield strengths. Powder yield stresses ranged from 3.0 Pa to 24.0 Pa of oscillatory stress. Compaction curves to 750 MPa found strong similarities in extrapolated yield point of stage I and II compaction for each of the powders (at approximately 500 MPa) suggesting that the variation in sulfate was greatest above the primary aggregate level. Scanning electron microscopy of samples at different states of shear in oscillatory rheometry confirmed the variation in the linear elastic region and the viscous flow regime.
A technique of this investigation was to approach aggregation via a novel perspective: aggregates are distinguished as being loose open structures that are highly disordered and stochastic in nature. The methodology used was to investigate the shear stresses required to rupture the various aggregation stages encountered and investigate the attempt to realign the now free-flowing constituents comprising the aggregate into a denser configuration. Mercury porosimetry was utilized to measure the pore size of the compact resulting from compaction via dry pressing and tape casting secondary scale aggregates. Mercury porosimetry of tapes cast at 0.85 and 9.09 cm/sec exhibited pore sizes ranging from 200-500 nm suggesting packing of intact micron-sized primary aggregates. Porosimetry further showed that this peak was absent in pressed pellets corroborating arguments of ruptured primary aggregates during compaction to 750 MPa.Ph.D.Includes bibliographical references (p. 166-170)
Design trends of low power thermal energy harvesting power management units
No full textThermal energy harvesting has gained attention in the last decade due to its promising possibilities in powering pervasive wireless sensor nodes, facilitating autonomous wireless sensor networks (WSN) for wide range of IoT (Internet of Things) applications. Thermal energy scavenging from waste heat can enable implementation of battery-less, zero-maintenance, place-and-forget electronic systems. Scavenging energy from the temperature difference between human body heat and ambiance is an attractive solution for powering wearables for continuous health monitoring, biomedical sensing and body area sensor networks (BASN). The low energy efficiency and low voltage output of the thermo-electric generators (TEG) pose challenges to the deployment of industry ready powering systems. These issues become more relentless, for energy scavenging from body heat using micro-TEGs, owing to the low temperature difference available. The low voltages generated by the transducers are ineffectual unless a power management converter system is incorporated to boost and regulate the voltage available to the load. The inherent inconsistent nature of the energy available from the ambience is yet another challenge to deal with. Hence, Energy Harvesting Power Management Units (EHPMU) are highly essential to integrate TEGs with commercial load systems. This chapter presents the challenges and recent trends in the design of integrated EHPMUs in CMOS (complementary metal-oxide-semiconductor) technology for harvesting thermal energy from low temperature difference environments. The state-of-the-art converter topologies in EHPMUs and recent trends in design of energy harvesting Integrated Circuits (IC) design are also discussed. © 2019 Nova Science Publishers, Inc
Parallelizing Unstructured Sparse Matrix Computations on Large-Scale Multiprocessors
No full textProblems in the class of unstructured sparse matrix computations are characterized by highly irregular dependencies and communication patterns that are not known at compile-time, but can be completely determined at run-time before the computations are actually performed. For this class of problems, current parallelizing compilers are unable to produce efficient code on large-scale distributed memory MIMD multiprocessors, and manual techniques are inflexible and too ad hoc to be generally effective.
In this thesis, we propose a run-time automatic partitioning and scheduling methodology for unstructured sparse matrix computations on large-scale multiprocessors. Our methodology is based on extracting information from the problem instance by preprocessing its symbolic structure, and using this information to achieve high performance in repeated iterations of the computations during which the symbolic structure is unchanged. We present efficient software tools to help users build their parallelization system by following this methodology.
We demonstrate the efficacy of our methodology on sparse Cholesky factorization, which has historically proven to be hard to parallelize. The highlight of our approach is a new two-dimensional block partitioning scheme. We build a run-time parallel system for block sparse Cholesky factorization called Sparse Hybrid Automatic Parallelization Environment (SHAPE), consisting of a parallel partitioner, a parallel scheduler and a parallel communication optimization algorithm. These are modular tools tied together by an explicit representation for block-based unstructured computations. We employ SHAPE to carry out an extensive experimental study of sparse Cholesky factorization on the iPSC/860. The experimental results show that with a judicious choice of partitioning parameters, our block-based partitioning and scheduling method outperforms a well-known column-based method in delivering high performance on a variety of structured and unstructured matrices. The preprocessing itself is shown to be very efficient, its cost being recovered in a small number of iterations of the factorization.
Our methodology and tools may be used to parallelize other unstructured sparse matrix computations for which the same symbolic structure is used in several iterations of the computations. Such computations include sparse triangular solution and sparse
matrix-vector multiplication.Technical report DCS-TR-30
SHAPE: A Parallelization Tool for Sparse Matrix Computations
No full textWe describe the design, implementation and performance of a Sparse Hybrid Automatic Parallelization Environment (SHAPE). SHAPE partitions and schedules sparse matrix computations for Cholesky factorization with the goal of achieving good performance at low cost, while providing flexibility for use as an experimental tool. It employs efficient parallelization algorithms which reduce the communication cost without adversely affecting the load balance by using a hybrid mixture of column and block partitions. Through several parameters, SHAPE aims for portability across a diverse range of sparse matrix structures and message-passing multiprocessors with different communication cost parameters. We present preliminary timing results on the iPSC/860 and compare the performance of SHAPE with that of a commonly used column-based method. The results show that SHAPE significantly reduces computation time, number of messages, and overall communication time for a variety of test matrices.Technical report dcs-tr-29
Supplementation of (Trigonella foenum-graecum L.) Fenugreek Leaves Stimulates the Insulin Action in Streptozotocin- Induced Diabetic Rats
No full textTrigonella foenum-graecum (Fenugreek) leaves exhibit antidiabetic and antioxidant properties. The present study was designed to elucidate the insulin stimulatory effect on supplementation of fenugreek leaves in streptozotocin-induced diabetes in rats. Supplementation of fenugreek leaves mixed with diet at doses of 0.5g and 1.0g/kg of body weight twice daily to diabetic rats for a period of 45days resulted in change in bodyweight, increase in weight of pancreas, enhances the insulin levels and a significant decrease in fasting blood glucose levels. Histopathological observations showed marked changes of the pancreas in treatment with the fenugreek leaves improved the functional state of the pancreatic β-cells and partially retained the damage caused by streptozotocin to the pancreatic islets. These findings of our study clearly indicate the insulin stimulatory effect of fenugreek leaves. The effect observed with the fenugreek leaves was better than that of glibenclamide (600 µg/kg bodyweight). ----------------------------------------------------------------------------------1Reader, Department of Biochemistry, Sathyabama University Dental College and Hospital, Chennai, Tamil Nadu, India2Director of Research, Ex-Dean of Science, Department of Biochemistry and Biotechnology, Annamalai University, Chidambaram*Corresponding author, Email: [email protected], Ph: +91-44- 24503064, Mob: +91-9244488676Cite This Article As:Annida Balakrishnan and Venugopal. P. Menon. 2010. Supplementation of (Trigonella foenum-graecum L.) Fenugreek Leaves Stimulates the Insulin Action in Streptozotocin- Induced Diabetic Rats. J. Ecobiotechnol. 2(3): 26-32
Automated System Partitioning for Efficient 3D Circuit Integration
No full textA Venn diagram comparing a computer, a car, an industrial robot and smart toaster would point to one piece of technology: the integrated circuit, or IC. Since the mid-20th century, it has grown omnipresent, evermore integrated and denser. The consumers' demand and industry relentless drive for more performance pushes the traditional technology to its last ditch. A short to mid-term solution to keep the trend going would be to stack layers of components, turning the IC 3D.If there are several tiers where elements are placed, one should take a decision regarding which component will occupy which layer, an endeavour regarded as a partitioning problem. It can be tackled by hand, but the size and complexity of modern systems require an automated approach so that the resulting partitions can be generated in accordance with optimisation objectives that tend to produce efficient results. This leads to automated system partitioning for efficient 3D circuit integration.Even though the problem has been studied for the past couple of decades, there is still a lot of open wondering: What is the grain at which we should consider the partitioning decision; should we consider each component individually or group them somehow beforehand? What is a good 3D partition and how does the hypergraph representation of the circuit impact its quality? How can we efficiently leverage information from a regular 2D circuit to take a partitioning decision? Is there an established advantage to automatically partition a system compare to a manual operation?To tackle those problems and achieve an automated system partitioning, we studied and developed a suite of methods that ingests a 2D description of a circuit and produces a 3D representation that can be further processed into a functional 3D IC.The proposed methodology leverages the information of a 2D placement by (1) extracting the design and its interconnectivity, (2) clustering the circuit to keep elements together as we deem more beneficial, (3) representing the system as a hypergraph and properly partition it according to optimisation objectives, and (4) generating files that represent our 3D circuit in such a fashion that it can be understood by other tools.This proposed partitioning flow supported a series of experiments to bring some answers to the various questions surrounding the field.Specifically, we showed that (1) there is an advantage to approaching a partitioning problem from a block-level rather than a gate-level perspective. In particular for benchmarked designs between 40k and 800k standard cells, with either local or global dominated interconnect, and with memory macros accounting for less than half the floorplan area or none at all, it appeared that around 2,000 geometric clusters was a sweet spot regarding the amount of wires cut and the total system wire-length they represent.Furthermore, we highlighted that (2) the choice of the clustering method applied before partitioning the system can have a significant impact on the partitioning quality and thus on the resulting 3D system performance, with up to 7% higher effective frequency compared to applying no clustering, and 4% better than the second best method tested.Finally, we studied that (3) automatically partitioning a circuit with large memory macros and templated cores has a tendency to keep each functional unit packed on the same die, similar to what a human might do manually, even if the partitioning is applied on a flattened gate-level netlist.Doctorat en Sciences de l'ingénieur et technologieinfo:eu-repo/semantics/nonPublishe
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