1,293 research outputs found
G.N. Itz: Stadsbouwmeester van Dordrecht 1832-1867
No full textDit boek bespreekt het leven en werk van G.N. Itz, stads bouwmeester van Dordrecht en zijn positie binnen de architectuurstromingen van de eerste helft van de negentiende eeuw. Een tijdvak dat tot nu toe in de architectuurgeschiedenis weinig aandacht heeft gekregen. G.N. Itz heeft vele bouwwerken ontworpen die heden ten dage nog het aanzicht van Dordrecht bepalen. Zo is de Korenbeurs en de Oud-Katholieke Kerk St. Maria Maior van zijn hand. Mede door de vele illustraties geeft dit boek een goed overzicht van de ontwerpen van G.N. Itz.Architectur
Direct numerical simulation of turbulent Couette-Poiseuille flow with zero skin friction
No full textThe near-wall scaling of mean velocity U(y) is addressed for the case of zero skin friction on one wall of a fully turbulent channel flow. The present DNS results can be added to the evidence in support of the conjecture that U is proportional to √yw in the region just above the wall at which the mean shear dU/dy = 0
Efficient Runtime Management of Reconfigurable Hardware Resources
No full textRuntime reconfigurable systems built upon devices with partial reconfiguration can provide reduction in overall hardware area, power efficiency, and economic cost in addition to the performance improvements due to better customization. However, the users of such systems have to be able to afford some additional costs compared to hardwired application specific circuits. More precisely reconfigurable devices have higher power consumption, occupy larger silicon area and operate at lower speeds. Higher power consumption requires additional packaging cost, shortens chip lifetimes, requires expensive cooling systems, decreases system reliability and prohibits battery operation. The less efficient usage of silicon real estate is usually compensated by the runtime hardware reconfiguration and functional units relocation. The available configuration data paths, however, have limited bandwidth that introduces overheads that may eclipse the dynamic reconfiguration benefits. In this dissertation, we address three major problems related to hardware resources runtime management: efficient online hardware task scheduling and placement, power consumption reduction and reconfiguration overhead minimization. Since hardware tasks are allocated and deallocated dynamically at runtime, the reconfigurable fabric can suffer of fragmentation. This can lead to the undesirable situation that tasks cannot be allocated even if there would be sufficient free area available. As a result, the overall system performance is degraded. Therefore, efficient hardware management of resources is very important. To manage hardware resources efficiently, we propose novel online hardware task scheduling and placement algorithms on partially reconfigurable devices with higher quality and faster execution compared to related proposals. To cope with the high power consumption in field programmable devices, we propose a novel logic element with lower power consumption compared to current approaches. To reduce runtime overhead, we augment the FPGA configuration circuit architecture and allow faster reconfiguration and relocation compared to current reconfigurable devices.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
The turbulent Ekman boundary layer over an infinite wind-turbine array
No full textA numerical simulation of a neutral turbulent Ekman layer containing an actuator disk array is performed, to improve the understanding of the coupling between the atmospheric boundary layer and large arrays of horizontal-axis wind turbines. An infinite array is represented by 64 disks in a periodic domain. The disks are represented by body forces and aligned with the time-dependent incoming flow. The same flow is also simulated with disks absent. Relative to the latter, the peak shear stress is doubled and located at the top of the disks; with a disk spacing of 5 diameters, the array efficiency is reduced to below 30%, in approximate agreement with the predictions of simple models approximating the turbines as roughness. The disks increase the boundary-layer depth, and the ratio of the ageostrophic to the geostrophic velocity component within the boundary layer, so that the Ekman spiral becomes more pronounced. These effects are required for the satisfaction of the global kinetic energy balance; the power output of the array is directly linked to the integral of the ageostrophic velocity over the boundary-layer depth. At disk height, the power extracted by the disks is locally balanced largely by the turbulent transport of mean flow kinetic energy. However, the increased turbulence kinetic energy production attributed to the disks is a large fraction of the power abstracted by them. The results suggest that mixed tower heights might be more efficient
Cultural-humanitarian cooperation as a tool of soft power: Case of Kazakhstan
No full textScientific novelty of the research determined by its purpose and objectives and is as follows:
- a series of actions has been proposed, taking into account the factors defined in the study, is capable of composing a strategic technology of “soft power”;
- resources and strategies of “soft power” were identified, a comparative analysis of the institutions of the US, EU, Russia and China conducting “soft power” was carried out, the role of the main factors in increasing the “soft power” of these states was assessed;
- the key features of cultural-humanitarian component of “soft power” of Kazakhstan were identified, the importance of taking into account the regional perception of states to increase the effectiveness of “soft power” strategies was proved;
- for the first time in Kazakhstani science,was made an attempt to consider science and education as the main tools of Kazakhstan’s “soft power”;
- relevant recommendations are proposed in the field of conceptual approaches to the formation of the strategy of “soft power” of the Republic of Kazakhstan;
- the author proposed his own theory (concept) called “power of attractiveness” (“representative power” “branding power”), which can be applied in the foreign policy of Kazakhstan for recognition, increasing the role, significance and image of the country in the international arena before having an impact on other countries
Tatar folk festivals and traditions through the eyes of a historian. To the 155th anniversary of scholar G.N. Akhmarov.
No full textThe name of Gaynetdin Nedzhmutdinovich Akhmarov (1864–1911) holds a spe-cial place among the scholars of the early 20th century due to his significant and multi-dimensional work. He is an educator, author of textbooks, historian, ethnographer, and public figure. The purpose of the paper is to explore the description of traditional Tatar customs and holidays in G.N. Akhmarov’s works. His historical analysis and explana-tion of the origin and development of folk traditions generates big interest not only in the academic circles, but among a broad audience of readers. The scholar’s works con-tain богатый материал on Tatar festivities. One particular work explores a Tatar wed-ding, which is shown as a national custom that has been formed over the course of many years. In his description of a Tatar wedding, the author provides its historical justification as he relies on his vast knowledge of history. G.N. Akhmarov uses this approach in the analysis of the Tatar holiday Sabantuy. The scholar reveals its history and conducts a comparative historical analysis with holidays of other Turkic peoples. The article exa¬mines the researcher’s view on other traditional festivities of Tatars
Architecture-Level Fault-Tolerance Techniques for Biomedical Implants
No full textIn this thesis the design and implementation of a new fault-tolerant architecture is described. The design targets both soft and hard faults by implementing a combination of known fault-tolerance tech niques in an efficient way. The proposed architecture allows a trade-off to be made between performance and fault tolerance by means of instruction-level configurability. The design is evaluated in terms of fault coverage, area, average power consumption, total energy consumption and performance for various duplication policies and test-sequence schedules. It is shown that an area and power overhead of roughly 25% and 32%, respectively, are required to implement the techniques on the baseline processor. The main overheads of the architecture are performance (up to 106%) and energy consumption (up to 157%). It is observed that the average power consumption is often reduced when a higher degree of fault tolerance is set and therefore the energy consumption does not increase linearly with a higher execution time. It is shown that test sequences can effectively be scheduled during program stalls, and that nearly 100% of all soft faults are tolerated by using instruction duplication. The main advantages of using our techniques are the flexibility to make a trade-off between the overheads and the required degree of fault tolerance, the high portability of the used techniques and the small increase in area and power consumption.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
All-fibre 0.4 mJ high-coherence eye-safe optical source
No full textWe report a narrow-linewidth band (FWHM 0.4nm) optical pulsed OPA (master oscillator- power amplifier) source emitting 0.412mJ pulses 1.5kW peak power) in the eye-safe range (@1548nm). Pulse duration and repetition rate were 90ns and 5kHz respectively
Exploring suitable Adder Designs for Biomedical Implants: A gracefully-degradable, fault-tolerant, and highly resource-constrained adder for SiMS
No full textModern applications demand extremely low power budgets in computer architectures for battery-operated devices. In the particular case of implantable devices —the main focus of this thesis— the system must have a long life span and batteries may not be possible or easy to recharge. In addition to power, chip area is also of major concern in this specific scenario. Since implantable devices are sometimes placed at locations inside the body where limited space is available, the implant must be as small as possible. The vast amount of volume of an implant is typically occupied by the battery and its electrodes, so the affordable chip area is very limited. Another reason why we want very small processor cores, is because this approach leaves more space for cache memory and it statistically reduces the chance of hardware failures. In this thesis we focus on the arithmetic unit (AU) of such a core, which is typically the adder/subtracter. The goal is to explore existing fault-tolerant and low-power AUs which are suitable for implementation in biomedical implants. A second objective is to study our own idea for a resource-constrained AU, based on graceful degradation: the so-called scalable arithmetic unit (ScAU). When an error occurs, the ScAU is able to proceed with the computational work, but no longer at the normal throughput: instead of single-cycle we downgrade to double-cycle operations. The design of our ScAU as well as several reference designs are all implemented in VHDL, synthesized and analyzed using Synopsys Design Compiler/PrimeTime and ModelSim. A major part of this thesis is dedicated to fault-tolerant design. An extensive study among common and less frequently employed error-detection schemes is performed. Finally, an error-detection scheme is chosen, applied to the ScAU, as well as to the reference designs for providing fair comparisons. A simple error-correction scheme is implemented as well. The fault-tolerant ScAU proves to have some very interesting advantages over the current state of the art. The fault-tolerant ScAU saves 17% of area, with a speedup of 12% for a 7.3% increase in power consumption, compared to the conventional technique with the lowest costs. Because of these savings, the power-delay-area product reduces by almost 21%. Under specific circumstances, our fault-tolerant ScAU is even capable of saving both area and power.Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Customizable Register Files for Multidimensional SIMD Architectures
No full textProcessor clock frequencies and the related performance improvements recently stagnated due to severe power and thermal dissipation barriers. As a result, the additional transistors provided by new technology generations are turned into more processing elements on a chip and used for their specialization towards power efficiency. For data parallel workloads the Single Instruction Multiple Data (SIMD) accelerators form a good example. SIMD processors, however, are notorious for turning performance programmers into low-level hardware experts. Moreover, legacy programs often require rework to follow (micro)architectural evolutions. This dissertation addresses the problems of SIMD accelerators programmability, code portability and performance efficient data management. The proposed Polymorphic Register File (PRF) provides a simple programming interface, allowing programmers to focus on algorithm optimizations rather than complex data transformations or low-level details. The overall PRF size is fixed, while the actual number, dimensions and sizes of its individual registers can be readjusted at runtime. Once the registers are defined, the microarchitecture takes care of the data management. We base our proposal on a 2D addressable multi-banked parallel storage, simultaneously delivering multiple data elements for a set of predetermined access patterns. For each pattern, we declare a Module Assignment Function (MAF) and a customized addressing function. We propose four MAF sets fully covering practical access patterns and evaluate them in a technology independent way. Next, we study a multi-lane, multi-port design and its HDL implementation. Clock frequencies of 100 to 300 MHz for FPGA and 500 to 900+ MHz for ASIC synthesis strongly indicate our PRF practical usability. For representative matrix computation workloads, single-core experiments suggest that our approach outperforms the Cell SIMD engine by up to three times. Furthermore, the number of executed instructions is reduced by up to three orders of magnitude compared to the Cell scalar core, depending on the vector registers size. Finally, we vectorize a separable 2D convolution algorithm for our PRF to fully avoid strided memory accesses, outperforming a state of the art NVIDIA GPU in throughput for mask sizes of 9 x 9 elements and bigger.Software and Computer TechnologyElectrical Engineering, Mathematics and Computer Scienc
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