1,721,243 research outputs found
Process simulations of a fabrication technology for detector compatible front-end circuits on high-resistivity silicon
This report describes the activity carried out to characterize, by means of a process
simulator, a technology (developed at ITC-irst in 1999) aimed at the production
of particle detectors with integrated front-end electronics. The main part of the
work has been dedicated to the calibration of the parameters involved in the simu-
lation of the implantation and diffusion steps. This has been carried out comparing
the calculated dopant profiles with a set of experimental data (SIMS, Spreading
Resistance, Capacitance-Voltage measurements). It has been evidenced that it is
extremely important to have dierent types of measurement for each layer in order
to obtain an accurate calibration. In general, satisfactory results have been achived,
and the simulated profiles can now be used to perform device simulations of the
transistors implemented in the layout. Furthermore, a calibrated process simulator
allows the definition of a new process flow with improved characteristic
Device Simulations of Isolation Techniques for Silicon Microstrip Detectors Made on p-Type Substrates
Recent studies have shown that silicon particle detectors made on p-type substrates feature an improved radiation hardness compared to more conventional single-side n-type devices. In particular, they show an increased charge collection efficiency at very high irradiation levels. At present few devices have been fabricated on these substrates and there are still many doubts regarding the best type of isolation structure to be employed for the interruption of the inversion electron layer present between the n+ electrodes. In this paper, a description of the behavior of microstrip detectors featuring three isolation solution (p-spray, p-stop and a combination between the previous two) is presented. The analysis is based on device simulations and covers the breakdown and interstrip capacitance issues
A new Silicon Photomultiplier structure for blue light detection
Silicon Photomultipliers are extremely promising devices for those applications requiring the detection of very low-intensity light (down to single photon detection). The major drawback of the existing prototypes is the poor detection efficiency, especially at short wavelengths (below 10% in the blue region). In this paper, a new structure aimed at improving this parameter at wavelengths ranging from 400–450nm is presented. With respect to a conventional structure it allows a maximization of the breakdown initiation probability for a given bias voltage and a reduction of the dead area. The analysis is supported by TCAD simulations
Improvements achieved in the fabrication of JFET transistors on high-resistivity silicon by means of TCAD simulations
The TCAD simulator is an indispensable tool both for the design of new devices based on semiconductor technology as well as for a thorough understanding of the device functioning. This paper reports the improvements achieved in the characteristics of JFET transistors built on high-resistivity silicon by exploiting the information extracted from process and device simulations to tune the fabrication technology. The first part of the report gives some examples of simulation outcomes already implemented in the fabrication process and the relative impact on the device performance, whereas the second presents possible improvements to be applied in the following productions to render the device more robus
Metodo di fabbricazione di un sensore a semiconduttore e sensore ottenuto Method of manufacturing a semiconductor sensor and sensor obtained
Interpolating silicon photomultipliers
We present the novel Interpolating Silicon PhotoMultiplier (ISiPM) concept which provides the spatial position of photon clusters with high resolution. Individual APD cells of the ISiPM area are not connected to a common readout electrode, but each cell is connected to one of several output channels. The most straight forward embodiment is a rectangular device with four outputs located (conceptually) in the corners. The assignment of each cell to one of the channels is chosen such that the center of gravity of an arbitrarily shaped group of cells can be reconstructed as (for instance) the weighted sum of the corner signals. Due to the finite size of the cells, this exact goal can only be approximated and residual systematical errors remain. A first prototype device with 100×100 cells on an area of 7.3×7.45 mm^2 has been fabricated at FBK and operated successfully. Individual LYSO crystals of ~2mm width in a block array can be identified easily. The ISiPM concept offers good spatial resolution on large areas with a moderate number of readout channels so that it is a promising device for instance for PET detectors
Overview on the main parameters and technology of modern Silicon Photomultipliers
In this paper, we give an overview of the main properties and technological implementation of densely packed
Single-photon Avalanche Diode arrays, which are commonly known as Silicon Photomultipliers, or SiPMs. These
detectors feature high internal gain, single-photon sensitivity, a high Photon Detection Efficiency, proportional
response to weak and fast light flashes, excellent timing resolution, low bias voltage, ruggedness and insensitivity
to magnetic field. They compare favorably to the traditional Photomultiplier Tube in several applications. In this
overview paper, we go through the SPAD/SiPM theory of operation, the modern SiPM implementations and the
typical technological options to build the sensor. This is done in conjunction with the description of the main
SiPM parameters, such as the Photon Detection Efficiency, the electrical properties, the primary and correlated
noise sources and the Single Photon Time Resolution
The DLED Algorithm for Timing Measurements on Large Area SiPMs Coupled to Scintillators
One of the main factors limiting the precision of timing measurements with silicon photomultipliers coupled to scintillators is the dark noise, especially in the case of large devices. In order to cope with it, a suitable signal processing should be employed. The method we propose is called differential leading edge discriminator (DLED) and allows an effective compensation of the baseline fluctuations due to the dark counts of the detector.
In this paper we show a comparison between the measurements
obtained using the traditional Leading Edge Discriminator technique
and the DLED. The improvement we observe is remarkable.
Combining this baseline correction algorithm with low temperatures,
we were able to reach a coincidence resolving time of 180 ps
FWHM, using 4mm x 4mm SiPMs produced at FBK coupled to
3.8mm x 3.8mm x 5 mm Teflon-wrapped LYSO crystals
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