296 research outputs found
E. W. Hofstee: Tussen speculatieve fantasie en empirisch realisme
No full textA dialogue with E. W. Hofstee, one of the Netherlands\u27 most distinguished social scientists, on the occasion of his seventieth birthday & his retirement as professor of sociology & sociography at the Agricultural U of Wageningen. The following are discussed: (1) his youth; (2) the influence of S. R. Steinmetz (1862-1940); (3) his PhD thesis; & (4) his academic career. Hofstee is renowned as a teacher, as a member of numerous boards, councils, & committees, & as an author of nearly 200 publications. Modified AA
Design space exploration for a Local Object Store
No full textNowadays, modern Integrated Circuit (IC) technology allows processor manufacturers to produce complex designs with up to a few billions of transistors.Technology limitations and the end of voltage and frequency scaling forced computer architecture to multicore designs and more specialized solutions on hardware. These technology trends increased memory bandwidth pressure, exposing modern computer systems to bandwidth limitations. Therefore, a large and increasing fraction of the area is occupied to efficiently manage the available memory bandwidth, especially the off-chip bandwidth. In addition, the failure of Dennard Scaling along with the end of multicore scaling gave rise to the Dark Silicon era, in which the percentage of transistors in an IC that can be simultaneously powered-on is decreasing. Thus, under a fixed power and thermal budget, decreasing the main memory accesses of a processor relieves operational costs and rises the potential for increased computing performance. In order to tackle this problem, we investigate the possibilities to offload functionalities of the software to hardware due to the drop in the cost of hardware. Based on our observations on modern programming languages, we formulate the hypothesis that object caching presents potential to advance the main processor's functionalities in handling objects which are the most commonly used memory structure in modern languages. After formulating the concept of a Local Object Store (LOS), this master thesis presents our progress on developing the framework for our proof of concept. A LOS is expected to decrease the number of main memory references by leveraging the "infant mortality" property of objects in real-life applications. Our proposed design provides support for the basic object manipulation operations while maintaining reference counters for the local objects.Therefore, comparing LOS with a cache memory, it permits the construction and destruction of short-lived objects without polluting the rest of the memory hierarchy. Our framework consists of a Smart Pointer library, two modified tracing tools that allow us to obtain traces from microbenchmarks, and a basic simulator for a Cache-LOS memory unit. Moreover, we develop and trace 3 microbenchmarks and using our framework simulate a 39% average reduction in the main memory accesses for a Cache-LOS memory architecture compared to a cache-only memory configuration. These promising results show the benefits of an integrated Cache-LOS to manipulate object structures.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Feeding High-Bandwidth Streaming-Based FPGA Accelerators
No full textA new class of accelerator interfaces has signi cant implications on system architecture. An order of magnitude more bandwidth forces us to reconsider FPGA design. OpenCAPI is a new interconnect standard that enables attaching FPGAs coherently to a high-bandwidth, low- latency interface. Keeping up with this bandwidth poses new challenges for the design of accelerators, and the logic feeding them.This thesis is conducted as part of a group project, where three other master students investigate database operator accelerators. This thesis focuses on the logic to feed the accelerators, by designing a recon gurable multi-stream bu er architecture. By generalizing across multiple common streaming-like accelerator access patterns, an interface consisting of multiple read ports with a smaller than cache line granularity is desired. At the same time, multiple read ports are allowed to request any stream, including reading across a cache line boundary.The proposed architecture exploits di erent memory primitives available on the latest genera- tion of Xilinx FPGAs. By combining a traditional multi-read port approach for data duplication with a second level of bu ering, a hierarchy typically found in caches, an architecture is pro- posed which can supply data from 64 streams to eight read ports without any access pattern restrictions.A correct-by-construction design methodology was used to simplify the validation of the design and to speedup the implementation phase. At the same time, the design methodology is doc- umented and examples are provided for ease of adoption. With the design methodology, the proposed architecture has been implemented and is accompanied by a validation framework.Various con gurations of the multi-stream bu er have been tested. Con gurations up to 64 streams with four read ports meet timing with an AFU request-to-response latency of ve cycles. The largest con guration with 64 streams and eight read ports fails timing. Limiting factors are the inherent architecture of FPGAs, where memories are physically located in speci c columns. This makes extracting data complex, especially at the target frequencies of 200 MHz and 400 MHz. Wires are scattered across the FPGA and wire delay becomes dominant.FPGA design at increasing bandwidths requires new design approaches. Synthesis results are no guarantee for the implemented design, and depending on the design size, could indicate a very optimistic operating frequency. Therefore, designing accelerators to keep up with an order of magnitude more bandwidth compared to the current state-of-the-art is complex, and requires carefully thought out accelerator cores, combined with an interface capable of feeding it.ISBN 978-94-6186-886-2Computer Engineerin
A Resiliency-First Approach to Distributed DAG Computations
No full textA framework is introduced for computations with transformations on immutable data. Inspiration is taken from Apache Spark, however the model of computation is generalized from an emphasis on narrow and wide dependencies, to an arbitrary set of transformations that form a directed acyclic graph (DAG). A distributed scheduling algorithm is developed with resiliency mechanisms that can account for stopping failure. Furthermore some properties of the system are derived. Finally future work is discussed showing there is fertile ground for further research and development to extend this work.Computer Engineerin
FPGA-Based High Throughput Merge Sorter
No full textAs database systems have shifted from disk-based to in-memory, and the scale of the database in big data analysis increases significantly, the workloads analyzing huge datasets are growing. Adopting FPGAs as hardware accelerators improves the flexibility, parallelism and power consumption versus CPU-only systems. The accelerators are also required to keep up with high memory bandwidth provided by advanced memory technologies and new interconnect interfaces. Sorting is the most fundamental database operation. In multiple-pass merge sorting, the final pass of the merge operation requires significant throughput performance to keep up with the high memory bandwidth. We study the state-of-the-art hardware-based sorters and present an analysis of our own design. In this thesis, we present an FPGA-based odd-even merge sorter which features throughput of 27.18 GB/s when merging 4 streams. Our design also presents stable throughput performance when the number of input streams is increased due to its high degree of parallelism. Thanks to such a generic design, the odd-even merge sorter does not suffer throughput drop for skewed data distributions and presents constant performance over various kinds of input distributions.Electrical Engineering | Microelectronic
Acceleration of the Chan-Vese model for 3D segmentation of tumors in CT scans using GPUs
No full textSegmentation and annotation of tumors in CT scans of the brain is a cumbersome time-consuming task for medical experts. Carefully annotated data can be used to build training data sets for machine learning frameworks, with the ultimate goal to fully automate this process. This thesis focuses on acceleration of the annotation process by implementation of an interactive accelerated segmentation model rather than implementation or evaluation of the machine learning part. The Chan-Vese model is an active contour model which can be used to detect objects for which the boundaries are not necessarily defined by gradient. An energy functional is minimized by evolvement of the contour. Evolvement of the contour in a numerical approximation, which uses finite differences and a level set formulation, is determined by solving a Partial differential equation (PDE) with an iterative solver. This thesis presents implementations for both 2D and 3D which use Successive over-relaxation (SOR) to solve the PDE. This computationally intensive task benefits from acceleration to keep the feedback loop, in the process of tuning parameters and convergence to the searched segmentation, as short as possible. The effect of varying the different parameters of the model are visualized for different examples images to allow for educated guesses. Accelerated implementations which leverage Compute Unified Device Architecture (CUDA) on a Graphics processing unit (GPU) are presented and compared to sequential and multithreaded OpenMP implementations. Evaluation of the CUDA implementations with single precision on a POWER8 platform with a K40 GPU shows a speedup of 56 and 107 over sequential implementations for 2D and 3D respectivelyComputer EngineeringComputer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Kinematics and stiffness of thermoformed plain-weave laminates: Simple models and experimental validation
No full textMechanical Maritime and Materials Engineerin
Acceleration of read alignment with coherent attached FPGA coprocessors
No full textWith the advent of Next Generation Sequencing (NGS), the cost of sequencing human DNA has decreased significantly over the past decade. This decrease in cost has attracted a great deal of attention from medical research and is now transitioning to clinical practice. Precision medicine, tailored to a persons's genetic profile, is becoming a viable option in the battle against cancer and rare genetic diseases. NGS sequencers produce millions of small fragments of DNA called reads. Mapping those reads to a reference genome proves to be a tremendous computational task and forms the bottleneck in current DNA analysis flows. BWA-MEM, a state-of-the-art alignment tool, applies the seed and extend paradigm to rapidly align the reads with a reference genome. The Smith-Waterman (S-W) algorithm is widely adopted by these state-of-the-art aligners. We have identified the S-W algorithm to be the main computational bottleneck on IBM's POWER8 processor. This recently released processor includes a new Coherent Accelerator Processor Interface (CAPI), that provides cache coherent access to shared memory for heterogeneous processors. We present a highly parallel FPGA-based accelerator that offloads the Smith-Waterman task. We have integrated the accelerator with software, relying on CAPI, in a tightly coupled fashion. This integrated heterogeneous system is able to achieve a speedup of 1.6X over purely software-based multithreaded execution of BWA-MEM. Furthermore, we propose a more general framework for dividing workload between the processor and accelerator in a fine-grained manner. We expect to achieve the maximum obtainable speedup (bounded by Amdahl's law) of 2X with the proposed framework.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
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