445 research outputs found
Engineering On-Chip Thermal Effects
No full textTemperature effects can be used to maliciously affect the behavior of
digital crypto-circuits. For example, temperature effects can create
covert communication channels, and they can affect the stability of
physical unclonable functions (PUFs). This talk observes that these
thermal effects can be engineered, and we describe two techniques. The
first technique shows how to filter the information through a covert
temperature channel. This leads to detectors for very specific events,
for example, someone touching the chip package. The second technique
shows how to mitigate the impact of temperature on a PUF design while
avoiding costly post-processing. We discuss the design of a compact
ring-oscillator PUF for FPGA which is tolerant to temperature
variations
The Rise of Hardware Security in Computer Architectures
No full textThis installment of Computer’s series highlighting the work published in IEEE Computer Society journals comes from IEEE Transactions on Computers
Computer Security at the Forefront of Emerging Topics in Computing
No full textSimilar to performance and power, security is a cross-cutting property that affects every abstraction level of computer design, from system conception down to physical implementation. However, unlike performance and power, security is not a physical quantity but a property of computing
Foundations of Secure Scaling (Dagstuhl Seminar 16342)
No full textThis report documents the program and the outcomes of Dagstuhl Seminar 16342 "Foundations of Secure Scaling". This seminar hosted researchers in secure electronic system design, spanning all abstraction levels from cryptographic engineering over chip design to system integration. We recognize that scaling is a fundamental force present at every abstraction level in electronic system design. While scaling is generally thought of as beneficial to the resulting implementations, this does not hold for secure electronic design. Indeed, the relations between scaling and the resulting security are poorly understood. This seminar facilitated the discussion between security experts at different abstraction levels in order to uncover the links between scaling and the resulting security
Secure Composition for Hardware Systems (Dagstuhl Seminar 19301)
No full textThe goal of the Dagstuhl Seminar 19301 ``Secure Composition for Hardware System'' was to establish a common understanding of principles and techniques that can facilitate composition and integration of hardware systems to achieve specified security guarantees.
Theoretical foundations of secure composition have been laid out in the past, but they are limited to software systems. New and unique security challenges arise when a real system composed of a range of hardware components, including application-specific blocks, programmable microcontrollers, and reconfigurable fabrics, are put together. For example, these components may have different owners, different trust assumptions and may not even have a common language to describe their security properties to each other. Physical and side-channel attacks that take advantage of various physical properties to undermine a system's security objectives add another level of complexity to the secure composition problem. Moreover, practical hardware systems include software of tremendous size and complexity, and hardware-software interaction can create new security challenges.
The seminar considered secure composition both from a pure hardware perspective, where multiple hardware blocks are composed in, e.g., a system on chip (SoC), and from a hardware-software perspective where hardware is integrated within a system that includes software. The seminar brought together researchers and industry practitioners from fields that have to deal with secure composition: Secure hardware architectures, hardware-oriented security, applied cryptography, test and verification of security properties. By involving industrial participants, we were able to get insights on real-world challenges, heuristics, and methodologies employed to address them and initiate a discussion towards new solutions
Fault injection as an attack vector against trustworthy embedded systems
No full textPresented on October 28, 2016 at 12:00 p.m. in the Pettit Microelectronics Research Building, MIRC Room 102Patrick Schaumont is a professor in Computer Engineering at Virginia Tech. His research interests are in design and design methods of secure, efficient and real-time embedded computing systems.Runtime: 55:37 minutesIn the Internet of Things, the cyber-world will use a huge number of small embedded computing elements to control and sense the real world. The integrity and trustworthiness of these embedded systems is crucial; their manipulation has direct consequences to the safety of the applications they support.
In this presentation we discuss the threat vector of implementation attacks on these embedded systems. We assume an adversary who can disturb the operation of such embedded systems by means of fault injection: the deliberate insertion of a computation error or memory error. This attack vector is realistic in cases when the embedded computing elements are subject to physical manipulation by an adversary. Fault injection can be achieved by pushing the embedded system outside of its nominal operating limits, which can be achieved by many different techniques.
We review the principles of fault injection, and highlight its use as a versatile hacking tool to obtain device control and to extract secret data. The traditional technique, differential fault analysis, dates back almost two decades, and many very effective variants have since been proposed. Most recently, biased-fault attacks have been developed which are able to use fault-response behavior as a side-channel signal. We review these biased fault attacks and explain why they are a threat to contemporary embedded designs. Finally, we show that biased-fault attacks apply equally well to software. We conclude that a fault attack can be engineered by an adversary to obtain a precise result
Protecting electronic information from theft and abuse is the goal of Virginia Tech CAREER research
No full textLearning to design computers so that personal and security information can be protected from theft or abuse is the goal of Virginia Tech College of Engineering researcher Patrick Schaumont, who has received a National Science Foundation (NSF) Faculty Early Career Development Program (CAREER) Award
Recommended from our members
Cross-Level Analysis of Side-channel Leakage Assessment
No full textSide-channel leakage assessment (SCLA) identifies unintended information leakage from hardware via power, timing, or electromagnetic emissions. Although traditionally performed post-silicon, pre-silicon SCLA enables early leakage detection through simulation across multiple design abstraction levels, including architecture, micro-architecture, and gate. This thesis introduces a simulation and analysis environment for performing pre-silicon SCLA across these abstraction levels, targeting RISC-V System-on-Chip (SoC) designs. We propose a methodology to identify two types of tracked components: leaky components, whose value changes depending on a Critical Security Parameter (CSP), and value-sensitive components, whose value directly depends on a CSP. Our approach uses both non-specific (e.g., TVLA) and specific (e.g., correlation-based) leakage tests. To support root-cause analysis, we automatically establish connections between components across abstraction levels and clock cycles, enabling the tracing of leakage propagation—even in pipelined designs. We evaluate our approach on the PicoRV32 and IBEX SoCs using benchmark programs and cryptographic operations. The results demonstrate improved leakage analysis capabilities, enabling the identification of both software- and hardware-level sources of leakage, including masking flaws and unintended register interactions in cryptographic implementations
A 10 Mbit/s Upstream Cable Modem with Automatic EqualizationPatrick Schaumont Radim Cmar Serge Vernalde Marc Engels
No full textA fully digital QAM16 burst receiver ASIC is presented. The BO4 receiver demodulates at 10 Mbit/s and uses an advanced signal processing architecture that performs perburst automatic equalization. It is a critical building block in a broadband access system for HFC networks. The chip was designed using a C++ based flow and is implemented as a 80 Kgate 0.7u CMOS standard cell design. 1 Introduction The widespread use of Internet is opening a pathway to emerging multimedia consumer networks and applications. These require a broadband data communications link to be established in the access network that connects the consumer to a core service network. The hybrid fiber-coax (HFC) access network that is currently in use for cable TV, is considered as an attractive candidate [4]. We have developed a chip that is embedded in an HFC head-end and that demodulates data transmitted from the consumer set-top. This chip is a fully digital burst receiver, characterized as shown in table 1. The chip..
Recommended from our members
Secure by Simulation: A Novel Timing-Driven Verification of Masked Hardware Designs
No full textMasking uses the principles of secret sharing as a countermeasure for side-channel leakage in digital logic circuits. It allows individual shares to leak independently without revealing the secret. In practice, however, masking shares often leak jointly due to implementation effects in the physical hardware. Circuit-level timing effects create glitches resulting from data dependent timing variations and are a source of side-channel leakage. Existing formal verification tools attempt to model hardware implementation effects as a means for leakage assessment. However, they are frequently based on the generally true properties of a circuit rather than the concrete implementation itself, leading to conservative masked implementations. This work presents a novel approach for masked circuit verification in the presence of glitches using low-level timing simulation. Timing simulation allows for concrete circuit implementation analysis while utilizing common-place chip design tools. Using detailed circuit timing models enables a highly accurate estimate of technology process variations’ impacts, including temperature and voltage, for robustly sized chip designs. The methodology presented in this work is able to quantify timing-based side-channel leakage for the circuit under test. Additionally, examples show the ability to distinguish between leaky and non-leaky masked designs that otherwise appear indistinguishable from traditional formal verification models. This work demonstrates that using circuit timing for masked hardware verification leads to a more efficient concrete circuit implementation and tighter leakage assertion
- …
