715 research outputs found

    A 110μW [110 mu W] 10Mb/s eTextiles transceiver for body area networks with remote battery power

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    A transceiver for communicating over an electronic textiles medium is implemented for body area networks. A supply-rail-coupled differential signaling scheme permits time-sharing of the eTextiles medium between communication and remote powering circuits. Fabricated in 0.18 μm [mu m] CMOS and operating at 0.9 V, the chip consumes 110 μW [mu W] at a data rate of 10 Mb/s over a 1 m fabric link.Semiconductor Research Corporation. Center for Circuits and Systems Solutions (Contract 2003-CT-888

    A 3 mm x 3 mm Fully Integrated Wireless Power Receiver and Neural Interface System-on-Chip

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    A miniaturized, fully integrated wireless power receiver system-on-chip with embedded 16-channel electrode array and data transceiver for electrocortical neural recording and stimulation is presented. An H-tree power and signal distribution network throughout the SoC maintains high quality factor up to 11 in the on-chip receiver coil at 144 MHz resonant frequency while rejecting RF interference in sensitive neural interface circuits owing to its perpendicular and equidistant geometry. A multi-mode buck-boost resonant regulating rectifier (<formula><tex>B2R3\text{B}^2 \text{R}^3</tex></formula>) offers greater than 11-dB input dynamic range in RF reception and less than 1 mV overshoot in transient load regulation. At 10 mm link distance, the 9 <formula><tex>mm2\text{mm}^2</tex></formula> neural interface SoC fabricated in a 180 nm silicon-on-insulator (SOI) process attains an overall wireless power transmission system efficiency (WSE) of 3.4% in driving a 160 μW load yielding a WSE figure-of-merit of 131, while maintaining signal integrity in analog recording and wireless data transmission that comprise the on-chip load.

    An energy-efficient all-digital UWB transmitter employing dual capacitively-coupled pulse-shaping drivers

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    This paper presents an all-digital, non-coherent, pulsed-UWB transmitter. By exploiting relaxed center frequency tolerances in non-coherent wideband communication, the transmitter synthesizes UWB pulses from an energy-efficient, single-ended digital ring oscillator. Dual capacitively coupled digital power amplifiers (PAs) are used in tandem to attenuate low frequency content typically associated with single-ended digital circuits driving single-ended antennas. Furthermore, four level digital pulse shaping is employed to attenuate RF sidelobes, resulting in FCC compliant operation in the 3.5, 4.0, and 4.5 GHz IEEE 802.15.4a bands without the use of any off-chip filters or large passive components. The transmitter is fabricated in a 90 nm CMOS process and occupies a core area of 0.07 mm2 . The entirely digital architecture consumes zero static bias current, resulting in an energy efficiency of 17.5 pJ/pulse at data rates up to 15.6 Mb/s.United States. Defense Advanced Research Projects Agency (DARPA) (HI-MEMS Contract FA8650-07-C-7704)Natural Sciences and Engineering Research Council of Canada (NSERC

    A 440pJ/bit 1Mb/s 2.4GHz multi-channel FBAR-based TX and an integrated pulse-shaping PA

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    A 2.4GHz TX in 65nm CMOS defines three channels using three high-Q FBARs and supports OOK, BPSK and MSK. The oscillators have -132dBc/Hz phase noise at 1MHz offset, and are multiplexed to an efficient resonant buffer. Optimized for low output power ≈-10dBm, a fully-integrated PA implements 7.5dB dynamic output power range using a dynamic impedance transformation network, and is used for amplitude pulse-shaping. Peak PA efficiency is 44.4% and peak TX efficiency is 33%. The entire TX consumes 440pJ/bit at 1Mb/s.Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation

    18.1 An Optically-Addressed Nanowire-Based Retinal Prosthesis with 73% RF-to-Stimulation Power Efficiency and 20nC-to-3μC Wireless Charge Telemetering

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    Recent approaches toward a functional retinal prosthesis to restore vision in neurodegenerative patients have been limited by the number of pixels that can be individually stimulated. The conventional approach, shown in Fig. 18.1.1 (left), uses an external camera to capture video, whose information is then wirelessly delivered to a hermetic housing (typically a titanium can) for conversion to N distinct stimulation pulses fed transocularly to an N-channel microelectrode array (MEA) placed epi- or subretinally. While this approach has proven long-term biocompatibility, translation to 1000s of channels with hermetic and durable transocular connections is not achievable with current technology, limiting existing designs to at most 256 channels, barely sufficient for 20/400 vision restoration [1] -[3]. Instead, recent work has suggested a full-CMOS solution, where an image sensor, stimulation circuits, and an MEA are integrated directly onto a single CMOS chip, thereby eliminating the interconnect challenge and providing a pathway to scalability [4], [5] (Fig. 18.1.1, middle). However, co-location of photoreceptors, amplifiers, and stimulation circuits imposes difficult fill-factor issues, while also significantly increasing heat dissipation near sensitive ocular and neural tissue due to the need to perform voltage regulation, amplification, and charge-balanced stimulation waveform generation (typical end-to-end efficiency of ~20%) right next to the retina. Most importantly, since the CMOS chip must also include electrodes and yet be sufficiently thin to fit epi- or sub-retinally, current encapsulation methods rely on thin-film deposition to enable patterned electrode windows, which has unproven long-term hemiticity or biocompatibility when encapsulating CMOS which has known biological toxins (e.g., copper), limiting practical implementation

    A 16-channel wireless neural interfacing SoC with RF-powered energy-replenishing adiabatic stimulation

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    This paper presents a fully-integrated 16-channel wireless neural interfacing SoC that employs an adiabatic stimulator powered directly from a 190-MHz on-chip antenna to eliminate bulky external components while simultaneously avoiding rectifier and regulator losses. Using a charge replenishing architecture, the stimulator outputs up to 145-μA, while achieving a 63.1% charge replenishing ratio and a stimulation efficiency factor of 6.0. Analog front-ends (AFEs) and telemetry circuitry are also included
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