177,157 research outputs found
Modeling reactive systems in java
No full textACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEM
Modeling reactive systems in java
No full textACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEM
Design Solutions For Modular Satellite Architectures
No full textThe cost-effective access to space envisaged by ESA would open a wide range of new opportunities and markets, but is still many years ahead. There is still a lack of devices, circuits, systems which make possible to develop satellites, ground stations and related services at costs compatible with the budget of academic institutions and small and medium enterprises (SMEs). As soon as the development time and cost of small satellites will fall below a certain threshold (e.g. 100,000 to 500,000 €), appropriate business models will likely develop to ensure a cost-effective and pervasive access to space, and related infrastructures and services. These considerations spurred the activity described in this paper, which is aimed at: - proving the feasibility of low-cost satellites using COTS (Commercial Off The Shelf) devices. This is a new trend in the space industry, which is not yet fully exploited due to the belief that COTS devices are not reliable enough for this kind of applications; - developing a flight model of a flexible and reliable nano-satellite with less than 25,000€; - training students in the field of avionics space systems: the design here described is developed by a team including undergraduate students working towards their graduation work. The educational aspects include the development of specific new university courses; - developing expertise in the field of low-cost avionic systems, both internally (university staff) and externally (graduated students will bring their expertise in their future work activity); - gather and cluster expertise and resources available inside the university around a common high-tech project; - creating a working group composed of both University and SMEs devoted to the application of commercially available technology to space environment. The first step in this direction was the development of a small low cost nano-satellite, started in the year 2004: the name of this project was PiCPoT (Piccolo Cubo del Politecnico di Torino, Small Cube of Politecnico di Torino). The project was carried out by some departments of the Politecnico, in particular Electronics and Aerospace. The main goal of the project was to evaluate the feasibility of using COTS components in a space project in order to greatly reduce costs; the design exploited internal subsystems modularity to allow reuse and further cost reduction for future missions. Starting from the PiCPoT experience, in 2006 we began a new project called ARaMiS (Speretta et al., 2007) which is the Italian acronym for Modular Architecture for Satellites. This work describes how the architecture of the ARaMiS satellite has been obtained from the lesson learned from our former experience. Moreover we describe satellite operations, giving some details of the major subsystems. This work is composed of two parts. The first one describes the design methodology, solutions and techniques that we used to develop the PiCPoT satellite; it gives an overview of its operations, with some details of the major subsystems. Details on the specifications can also be found in (Del Corso et al., 2007; Passerone et al, 2008). The second part, indeed exploits the experience achieved during the PiCPoT development and describes a proposal for a low-cost modular architecture for satellite
3DV — An embedded, dense stereovision-based depth mapping system
No full textThis paper describes the architecture and hardware implementation of an embedded, low-cost and low-power dense stereo reconstruction system, running at 30 fps at VGA resolution. The processing pipeline includes an initial image rectification stage, a cost generation unit based on the non-parametric census transform, a state-of-the-art Semi-Global cost optimization stage, and a final minimization and noise suppression step. The hardware implementation is based on a Xilinx ZynqTM System-on-Chip, which besides the FPGA provides a physical dual-core ARM CPU, which is exploited for control and to deliver output over the integrated Gigabit Ethernet connection
Circuit Design and Power Consumption Analysis of Wireless Gas Sensor Nodes: One-Sensor versus Two-Sensor Approach
No full textWireless sensor networks (WSNs) have recently been applied in industrial monitoring applications including hazardous gases detection. As a major power consumer of a node, gas sensors may significantly constrain its lifetime. Hence, the sensing circuit must be carefully designed to optimize performance and retain accuracy. In this paper, we propose for the first time the principle of gas concentration measurement based on a single sensor in a voltage divider circuit, instead of the well-known Wheatstone bridge sensing circuit, which employs two sensors. We discuss the design of a real WSN node for gas sensing and evaluate it with respect to an identical platform that uses the Wheatstone bridge. The proposed approach ensures significant energy savings and helps to avoid zero offset issue. Besides, we employ a more efficient and secure sensor heating profile; it does not damage the sensor and does not make gas sensing dependent on environmental conditions. Experimental results show a 30% reduction in power with respect to the state-of-the-art
Design and implementation of the control structure of the PAPRICA-3 processorProceedings of 4th Euromicro Workshop on Parallel and Distributed Processing
No full textA High Speed VLSI Architecture for Handwriting Recognition
No full textThis article presents PAPRICA-3, a VLSI-oriented architecture for real-time processing of images and its implementation on HACRE, a high-speed, cascadable, 32-processors VLSI slice. The architecture is based on an array of programmable processing elements with the instruction set tailored to image processing, mathematical morphology, and neural networks emulation. Dedicated hardware features allow simultaneous image acquisition, processing, neural network emulation, and a straightforward interface with a hosting PC. HACRE has been fabricated and successfully tested at a clock frequency of 50 MHz. A board hosting up to four chips and providing a 33 MHz PCI interface has been manufactured and used to build BEATR IX, a system for the recognition of handwritten check amounts, by integrating image processing and neural network algorithms (on the board) with context analysis techniques (on the hosting PC)
An industrial case study using an MBE approach: from architecture to safety analysis.
No full textWe discuss the initial phases of software development of a real industrial safety-related device in the railway application domain. In particular, to achieve greater confidence in the system, we illustrate the development of the system architecture (using a standard model domain-specific language), the computation of the safety integrity level and the calculation of the reliability of the whole system. We reiterate the safety analysis on the sub-systems. The proposed methodology has found immediate industrial applications
Correctness in the Specification and Handling of Non-functional Attributes of High-Integrity Real-Time Embedded Systems
No full textIn high-integrity systems, the focus of the development
process is geared to assuring that the assertions made on
the system are both correct (i.e., semantically sustainable) and feasible (i.e., true at run time). Some of those assertions take effect in the non-functional domain, that is, in how the system is realized and behaves in time, space and communication during execution; others in the functional domain, and thus concern what outputs the system produces for its inputs. In this paper, we address the problem of achieving correct specification and handling of non-functional attributes, with particular regard to the concurrent structure of the system, the safeness of the interaction protocols engaged in it, and the guarantee that its timing feasibility can be statically verified. Our approach is based on a Model-Driven Engineering methodology, in which correctness can be ensured by construction or verified at a high level of abstraction, while the runtime implementation structure and code are automatically generated. We employ the Ravenscar Computation Model (RCM) and focus, in particular, on aerospace applications, which impose stringent requirements on correctness properties. We discuss an algebraic formalization of our model based on graph theory which we
use to prove safe termination in systems compliant with RCM, and show how to use the MAST+ static analyzer to verify the timing aspects. We finally illustrate the results of a prototype tool that was developed for evaluation by major industrial players in the European space industry
- …
