1,720,991 research outputs found
A robust, power- and area-efficient gm-control for low-noise operational amplifiers
No full textThis paper presents an efficient and robust circuital implementation of a rail-to-rail input stage with transconductance control, tailored for low-noise operational amplifiers based on differential pairs biased in the sub-threshold region. The proposed gm-control circuit design is indeed based on transistors ratio only, and allows efficient control with scaled currents and dimensions. The architecture guarantees nearly constant performance in terms of bandwidth and power consumption over the whole common mode input range in a power- and area-efficient way. The achievable precision of the transconductance control is also analyzed with transistor equations and its deviation predicted with a simple analytical model, which suggests also a strategy for the minimization of the error by proper tuning. A prototype of the input–output rail-to-rail operational amplifier has been fabricated in a standard 0.35 μm CMOS technology, confirming the validity of the gm-control loop. The amplifier consumes 597 μA from a 3.3 V supply, with an open-loop gain of 107 dB and a gain-bandwidth product of 42.6 MHz
A compact QRNG for IoT applications
No full textThe present paper describes a new QRNG based on the arrival time of photons. The device needs an external light source to fully control the generation of random bit. This allows to ensure an almost constant data rate, regardless possible environmental parameter variations, and a minimization of the contribution of other unwanted sources of noise (DCR). To increase the output rate, the QRNG is split up into several e lementary generators organized in an array working simultaneously. Moreover, an embedded post-processing block allows to improve the output entropy for a high quality random sequence. The device, now under test, has been designed in a standard 150nm CMOS technology. Preliminary results showed an average activity of about 30 Mbps (raw data)
A SPAD-Based Optical Encoder
No full textThis paper reports on a proof-of-concept SPAD-based (Single Photon Avalanche Diode) optical encoder. The work aims at demonstrating the advantages of SPADs over photodiodes, which are typically used in the current optical position measuring systems. In addition to their high sensitivity and high speed, SPADs allow fully digital signal processing, offering a large system flexibility and scalability toward advanced CMOS technologies. Preliminary tests have been carried out using an array of 100 x 100 SPADs, coupled with an optical Gray-coded disk and a laser diode. Binary frame sequences were acquired and processed off-line through a lightweight algorithm to reproduce the disc code. The described algorithm aims at being integrated in the same chip of the sensor to speed up the signal processing chain, thus allowing high rotation speeds to be achieved. Experimental results are reported, together with future work and conclusions
Single-Photon Imagers with In-Pixel, Area-Efficient Time-to-Digital Converters
No full textSingle-photon avalanche diodes in CMOS technology are a key enabling technology for the realization of monolithic time-resolved image sensors for a broad range of applications. By combining avalanche detectors with integrated logic for counting and timestamping, photon arrays can extract the spatiotemporal characteristics of an optical signal in the spatial and temporal domains. This chapter focuses on the implementation of two sensor architectures with in-pixel, area-efficient time-to-digital converters with integrated ring-oscillator. The first design is based on a timestamping circuit with analog oversampling of the ring phases, achieving 19.46% fill factor. The second design implements the smallest ring-oscillator in the literature (12 transistors only), and its scalability has been demonstrated in a 60 k pixel array
Avalanche-mode High Frame Rate, Low Light CMOS Single Photon Image Sensors
No full textOur recent progress in CMOS single-photon avalanche diode (SPAD) image sensors will be presented. We will highlight areas where these can compete with existing low-light imaging technologies using examples from superresolution microscopy. Article not available
A 500 x 500 Pixel Image Sensor with Multiple Regions of Interest for Center of Mass-Based Event Detection
No full textThis article reports on a 500×500 pixel CMOS vision sensor allowing multiple regions of interest (RoIs) per frame with programmable and arbitrary number, size, and shape, aimed at minimizing the delivered data and at reducing the required amount of off-chip computation. In the proposed application, the center of mass (CoM) terms of the RoIs, computed by the sensor, are used to monitor the activity in some zones of the scene to switch the sensor to a pixel delivering mode, enabling high-level image processing upon request through an external processing platform. Anomalies are detected as changes in the x–y position of the CoM. The embedded CoM processor (CoMP) extracts the centroid terms of the selected subwindows, managing a maximum RoI size of 128×128 pixels. The parameters of each RoI are uploaded rowwise through a serial interface (SI). The sensor with 8- μ m pixel pitch is manufactured in a 110-nm 1P4M CMOS technology and occupies 25 mm2. The chip, operating in standard imaging mode (IM), consumes 4.9 mW at 20 fps
A 500 × 500 Pixel Image Sensor with Arbitrary Number of RoIs per Frame and Image Filtering for Center of Mass Estimation
No full textThis paper reports on a 500 x 500 pixel CMOS image sensor allowing multiple Regions of Interest (RoI) per frame with programmable number and size, aimed at minimizing the amount of data to be delivered off-chip and at reducing its power consumption. The proposed sensor architecture offers large flexibility to face different use case scenarios and it is suitable to any pixel array. The sensor embeds image background subtraction capability and integrates a computing layer which pre-filters the pixels to estimate the Center of Mass (CoM) of the RoIs up to a maximum size of 128 x 128 pixels. The 8 μm pixel sensor is manufactured in a 110 nm 1P4M CMOS technology and occupies 25 mm2. The chip, operating in standard imaging mode, consumes 4.9 mW at 30 fps
A 32x 32-Pixel CMOS Imager for Quantum Optics With Per-SPAD TDC, 19.48% Fill-Factor in a 44.64-μm Pitch Reaching 1-MHz Observation Rate
No full textThis article reports the design and characterization of a 32 × 32 single-photon avalanche diode (SPAD) time-resolved image sensor for quantum imaging applications fabricated in a 150-nm CMOS standard technology. A per-SPAD time-to-digital converter (TDC) records the spatial cross correlation functions of a flux of entangled photons. Each 44.64- μm pixel with 19.48% fill-factor features a 210.2-ps resolution, 50-ns (8-bit) range TDC with 1.28-LSB differential and 1.92-LSB integral nonlinearity (DNL/INL). The sensor achieves an observation rate of up to 1 MHz through a current-based mechanism that avoids reading empty frames when the photon rates are low. A row-skipping mechanism detects the absence of SPAD activity in a row to increase the duty cycle. These two features require only three transistors in each pixel. The sensor functionality is demonstrated in a quantum imaging experiment that achieves super-resolution
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