1,721,024 research outputs found
Periodicity as Condition to Noise Robustness for Chaotic Maps with Piecewise Constant Invariant Density
No full textChaotic maps represent an effective method of generating random-like sequences, that combines the benefits of relying on simple, causal models with good unpredictability.
However, since chaotic maps behavior is generally strongly dependent on unavoidable implementation errors and external perturbations, the possibility of guaranteeing map statistical robustness is of great practical concern.
Here we present a technique to guarantee the independence of the first-order statistics of external perturbations, modeled as an additive, map-independent random variable.
The developed criterion applies to a quite general class of maps
A macro-model for the efficient simulation of an ADC-based RNG
Full text linkIn this paper we present a macro-model for a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35μm CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests to assure the quality of the output stream. © 2005 IEEE
A 3 GHz spread spectrum clock generator for SATA applications using chaotic PAM modulation
Full text linkThis paper proposes a prototype of a Spread Spectrum Clock Generator which is the first known specifically meant for 3 GHz Serial ATA-II applications. The modulation is obtained from a fractional PLL which employs a Delta-Sigma modulator. A further innovative aspect of our work is that our prototype takes advantage of a chaotic PAM as driving signal, instead a triangular signal as in all spread spectrum generators proposed in literature for SATA-II. In this way we avoid the periodicity of the modulated clock, completely flattening the peaks in the power spectral density. The circuit prototype has been designed n 0.13 μm CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW = 100 kHz. The chip active area is 0.27×0.78 mm2 and the power consumption is as low as 14.7 mW. © 2008 IEEE
Second-level NIST randomness tests for improving test reliability
Full text linkTesting Random Number Generators (RNGs) is as important as designing them. Here we consider the NIST test suite SF 800-22 and we show that, as suggested by NIST itself, to reveal non-perfect generators a more in-depth analysis should be performed using the outcomes of the suite over many generated sequences. Testing these second-level statistics is not trivial and, relying on a proper model that takes into account the errors due to the approximations in the first level tests, we propose a tuning of the parameters in the simplest cases. The validity of our consideration is widely supported by experimental results on several RNG currently employed by major IT players, as well as a chaos-based RNG designed by authors
On the Approximation Errors in the Frequency Test Included in the NIST SP800-22 Statistical Test Suite
Full text linkIn previous papers we have addressed the problem of testing Random Number Generators (RNGs) through statistical tests, with particular emphasis on the approach we called second-level testing. We have shown that this approach is capable of achieving much higher accuracy in exposing non-random generators, but may suffer from reliability issues due to approximations introduced in the test. Here we consider the NIST Frequency Test and present a mathematical expression of the error introduced by approximating the effective discrete distribution function with its continuous limit distribution. The matching against experimental data is almost perfect. © 2008 IEEE
A 65nm continuous-time sigma-delta modulator with limited OTA DC gain compensation
Full text linkThis paper explores the effects of compensating the performance degradation in high-speed Continuous-Time Sigma-Delta modulators when the loop integrators are implemented through limited gain Operational Transconductance Amplifiers. Yet, the low DC-gain strongly affects both integrator magnitude and phase responses, with a reduction in the overall effective number of bits. This work models the degradation as due to a signal-dependent memory-less perturbation and theoretically studies its compensation by feeding an opposite signal back to the integrator input. The implementation and experimental results on a 65nm CMOS 2nd order prototype evaluate the performance increase with this technique, where no other compensation, nor any digital calibration, is included. Tested in different conditions, the compensated prototype improves more than 1.5 bit the ENoB with respect to the uncompensated counterpart. For a sampling frequency of 500 MHz the power consumption is 1.7mW, resulting in a 477.2fJ/conv-lev Walden and a 148.8dB Schreirer Figures of Merit
Noise robustness condition for chaotic maps with piecewise constant invariant density
Full text linkChaotic maps represent an effective method for generating random-like sequences, that combines the benefits of relying on simple, causal models with good unpredictability. Regrettably such positive features are counterbalanced by the fact that statistics of true-implemented chaotic maps are generally strongly dependent on implementation errors and external perturbations. Here we study the effect of an external, additive, map-independent noise perturbation in the map model, and present a technique to guarantee, for a quite large class of maps, independence of the first-order statistics of the noise features
Second-level testing revisited and applications to NIST SP800-22
Full text linkThe use of second-level testing to reduce Type II errors in RNG validation was suggested from the very beginning though rarely employed in real-world cases. Yet, as security requirements become more critical and the availability of even faster RNG more commonplace, second-level testing will be key to distinguishing RNGs based on the quality of very large chunks of their output. This paper addresses some principles governing the proper design of second-level tests (i.e. how to divide available data into chunks and how to compute second-level p-values) as well as its implications on the design of the underlying basic tests. © 2007 IEEE
A Zero-Transient Dual-Frequency Control for Class-E Resonant DC-DC Converters
Full text linkIn this paper, a dual-frequency control method for regulating the output power in class-E resonant DC-DC converters has been introduced. As in the standard ON-OFF control or other recently proposed dual-frequency controls, the approach is based on the ability of the converter to alternately operate in a high- and a low-power state. The proposed solution has a twofold advantage: on the one hand, soft-switching capabilities (i.e., Zero-Voltage and Zero-Voltage-Derivative switching) are preserved in both operating states; on the other hand, it is possible to reduce to zero the transient time required to switch from one state to the other one. The most straightforward consequence is the possibility to increase to very large values the frequency at which the two operating states are switched, up to the same order of magnitude as the main switching frequency of the converter. In this way, the additional ripple introduced by the proposed dual-frequency control can be decreased to a negligible value. The approach has been validated by measurements on a prototype operating between 4 MHz and 8 MHz and in which it has been possible to increase the control frequency up to 500 kHz
Adapted Compressed Sensing: A Game Worth Playing
Full text linkDespite the universal nature of the compressed sensing mechanism, additional information on the class of sparse signals to acquire allows adjustments that yield substantial improvements. In facts, proper exploitation of these priors allows to significantly increase compression for a given reconstruction quality. Since one of the most promising scopes of application of compressed sensing is that of IoT devices subject to extremely low resource constraint, adaptation is especially interesting when it can cope with hardware-related constraint allowing low complexity implementations. We here review and compare many algorithmic adaptation policies that focus either on the encoding part or on the recovery part of compressed sensing. We also review other more hardware-oriented adaptation techniques that are actually able to make the difference when coming to real-world implementations. In all cases, adaptation proves to be a tool that should be mastered in practical applications to unleash the full potential of compressed sensing
- …
