1,720,969 research outputs found
Electrical characterization of Trough Silicon Via (TSV) depending on structural and material parameters based on 3D full wave simulation
No full textThis work was supported by the IT R&D program of MIC/IITA. [2005-S-118-02, Development of High-Performance and Smallest SiP Technology
Differential signal via shield with narrow via pitch partial electromagnetic bandgap structure
No full text
Modeling and measurement of simultaneous switching noise coupling through signal via transition
No full textThe signal via is a heavily utilized interconnection structure in high-density System-on-Package (SoP) substrates and printed circuit boards (PCBs). Vias facilitate complicated routings in these multilayer structures. Significant simultaneous switching noise (SSN) coupling occurs through the signal via transition when the signal via suffers return current interruption caused by reference plane exchange. The coupled SSN decreases noise and timing margins of digital and analog circuits, resulting in reduction of achievable jitter performance, bit error ratio (BER), and system reliability. We introduce a modeling method to estimate SSN coupling based on a balanced transmission line matrix (TLM) method. The proposed modeling method is successfully verified by a series of time-domain and frequency-domain measurements of several via transition structures. First, it is clearly verified that SSN coupling causes considerable clock waveform distortion, increases jitter and noise, and reduces margins in pseudorandom bit sequence (PRBS) eye patterns. We also note that the major frequency spectrum component of the coupled noise. is one of the plane pair resonance frequencies in the PCB power/ground pair. Furthermore, we demonstrate that the amount of SSN noise coupling is strongly dependent not only on the position of the signal via, but also on the layer configuration of the multilayer PCB. Finally, we have successfully proposed and confirmed a design methodology to minimize the SSN coupling based on an optimal via positioning approach
Sharing power distribution networks for enhanced power integrity by using through-silicon-via
No full textThis work was supported by the IT R&D program of
MIC/IITA [2005-S-118-02, Development of High-
Performance and Smallest SiP Technology] and the Brain
Korea 21 project [the School of Information Technology,
KAIST in 2008]
Wideband low power distribution network impedance of high chip density package using 3-D stacked through silicon vias
No full textA frequency tunable resonant clock distribution scheme using bond-wire inductor
No full textThis work was supported by the IT R&D program of
MIC/IITA. [2005-S-118-02, Development of High-
Performance and Smallest SiP Technology
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