1,720,969 research outputs found
Injection locked ring oscillator based digital-to-time converter and method for providing a filtered interpolated phase signal
No full textApparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase interpolator can be configured to receive digital representations of two or more distinct phase signals, and to interpolate the digital representations of the two or more distinct phase signals to provide an interpolated output phase signal. The ring oscillator can be configured to receive the interpolated phase signal, to lock on to a frequency and a phase of the interpolated output phase signal, and to provide a filtered phase signal
Analysis of a Three-Way Voltage-Mode Digital Doherty Power Amplifier for Bluetooth Applications
No full textAnalysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers
No full textThis paper presents the design of a matching network (MN) for switched-capacitor PAs (SCPA) optimized for efficiency against required load output power. The presented third-order MN exploits the intrinsic output capacitance of the SCPA, reducing the number of passive components required by the MN. As an example, a MN for a 1.1 V switched capacitor power amplifier has been designed with a bluetooth application in mind. The example MN has been implemented in a 28 nm CMOS RF metal stack and provides 16.7 dBm output power with IL = 1.1 dB at 2.4 GHz in an area of 300 x 300 um^2 when resonated by an SCPA capacitance of 2.3 pF. Further structures have then been implemented and characterized, covering a broader set of applications
Design strategies for SOI FinFET Low-Noise Amplifiers: dealing with Flicker Noise
No full textThe trade-off between gate length (Lgate), flicker noise and powder consumption in Low-Noise-Amplifiers (LNA) designed with 45nm FinFETs (FFs) has been investigated, in order to draw new design guidelines for this novel technology. The simulation results highlight the existence of an optimum Lgate which reduces the impact of flicker noise at minimum power consumption
A 0.7-V Multiclass Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22-nm CMOS
No full textThis letter presents a multiclass, asymmetric digital Doherty power amplifier (DDPA) for Bluetooth low energy (BLE) applications, that achieves high efficiency at full-scale as well as at 8.6-dB back-off using a single 0.7-V supply voltage. The proposed DDPA is made of two power-combined switched-capacitor power amplifiers (SCPAs) and uses an on-chip, compact matching network. The DDPA is implemented in a 22-nm bulk CMOS technology, with the main goal of supporting BLE power classes 1.5, 2, and 3 efficiently. The proposed DDPA shows a peak drain efficiency (DE) of 41% at 10.5-dBm full-scale output power, and features an output spectrum compliant with the BLE spectrum emission mask
Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers
No full textThis article analyzes the behavior of a single supply asymmetric Doherty power amplifier, made of two switched-capacitor power amplifiers (SCPAs) and a power combining network. The proposed analysis shows that there is an optimal power partition between the two SCPAs that maximizes the efficiency at each output power level. The optimal control of the PA leads to two power back-off (PBO) efficiency peaks, whose magnitude depends on the size of the switches of each SCPA and on the matching network design. The optimization of both switch sizing and output network design is carried out analytically. The achieved theoretical results are then verified by transistor-level simulations. They have also been validated by measurements performed on a prototype, fully integrated in a commercial 22-nm CMOS technology, at an operation frequency of 2.3 GHz
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs
No full textA Matching Network for a 1.1V Switched Capacitor Power Amplifier has been designed with a Bluetooth Application in mind. The Matching Network has been implemented in a 28nm CMOS RF Metal Stack and provides 16.7dBm output power with IL = 1.1dB at 2.4GHz. A detailed analytical model of power and efficiency of the Matching Network is derived and used for optimal design of the Matching Network. The model shows very good agreement with circuit simulations, and good matching with experimental data as well
A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner
No full textThis paper presents a DPA design with a DAT power combiner drawn in the package metallization achieving 26.7dBm maximum output power at 25% PAE using 0.5mm 2 area on die and 0.5mm 2 on package. Thanks to an offline static 2D DPD, an EVM as low as 4.1%at 17.3dBm modulated output power is achieved for a WIFI 2x20MHz, and an EVM of 1.8% at 14.3dBm for a WIFI 20MHz signal is achieved, enabling up to QAM-256 support
LC-Oscillator featuring independent Gate biasing implemented in 32 nm CMOS technology
No full textThis paper analyzes the potentials and the limitations of a novel LC-Oscillator topology featuring independent gate biasing. The topic is addressed from an experimental perspective. The novel topology has been implemented in a state-of-the-art 32 nm CMOS technology and used as a proof-of-concept. The performance of the oscillator has been evaluated in terms of power consumption and phase-noise. The independent gate biasing helps in relaxing the noise/power trade-off that limits the performance of conventional LC-Oscillators
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