1,721,510 research outputs found
Floating Gate devices: operation and compact modeling
No full textThis paper describes a possible approach to Compact Modeling of Floating Gate devices. Floating Gate devices are the basic building blocks of Semiconductor Nonvolatile Memories (EPROM, EEPROM, Flash). Among these, Flash are the most innovative and complex devices. The strategy followed developing this new model allows to cover a wide range of simulation conditions, making it very appealing for device physicists and circuit designers
Statistical Simulations of Oxide Leakage Current in MOS Transistors and Floating Gate Devices
No full textThe purpose of this paper is to illustrate a physically-based model allowing the statistical simulations of oxide leakage currents in MOS transistors and Floating Gate memories. This model computes the leakage current through defects randomly generated in the oxide, in case accounting for the formation of percolation paths. Furthermore, a calculation procedure has been developed to calculate the threshold voltage of FG memories from simulated oxide leakage currents in some reliability conditions, thus allowing to investigate their actual Flash data retention issues and their future trends. To this regards, it will be shown how this simulation model can be used to investigate threshold voltage shift occurring in retention conditions in FG memories after both Program/erase cycles, i.e. electrical stress and radiation exposure
A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) Current Suitable for Compact Modeling
No full textThis paper presents for the first time a new approach to hot-carrier phenomena leading to an analytical model of both Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) currents. This model can be incorporated in Spice-like models of MOS transistors and Floating Gate (FG) devices to include hot carrier phenomena also in circuit simulations
Flash Memories
No full textThis paper provides an overview of Floating Gate technology, the architectures used in it, and the major applications in which it is found. New technologies and devices are discussed and compared to industry standard devices
Statistical simulations for flash memory reliability analysis and prediction
No full textIn this paper, through the use of a recently proposed statistical model of stress-induced leakage current, we will investigate the reliability of actual Flash memory technologies and predict future trends. We investigate either program disturbs (namely gate and drain disturbs) and data retention of state-of-the-art Flash memory cells and use this model to correlate the induced threshold voltage shift to the typical outputs coming from oxide characterization, that are density, cross section, and energy level of defects. Physical mechanisms inducing the largest threshold voltage (V-T) degradation will be identified and explained. Furthermore, we predict the effects of tunnel oxide scaling on Flash memory data retention, giving a rule of thumb to scale the tunnel oxide while maintaining the same retention requirements
Improving reliability and safety of automotive electronics: research activities within the PROMETHEUS project
No full textMicroelectronics systems designed for automotive applications face an extremely hostile electrical and physical environment. Designers must produce increased component and system reliability while maintaining required compactness and cost effectiveness levels. Their designs become crucial to all as we devote more electronic systems to safety-critical applications. We summarizee the results of the European Prometheus PRO-CHIP research groups working on the reliability and fail-safe operation of microelectronic systems and devices
Statistical simulations to inspect and predict data retention and program disturbs in Flash memories
No full textA new statistical model of stress-induced leakage current (SILC) is implemented and used to predict data retention and program disturbs of state-of-the-art flash memories, and to correlate oxide characterization outputs (density, cross section, energy level of defects) to flash memory reliability. Physical mechanisms inducing the largest threshold voltage (VT) degradation are explained, and tunnel oxide scaling effects on flash reliability are predicted
Introduction to the Special Issue on Nonvolatile Memory Reliability, IEEE Transactions on Device and Materials Reliability
No full textThis Special Issue of the IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY is intended to give a com- prehensive picture of the state-of-the-art in the field of non- volatile memories. It is an important opportunity for the NVM technical community to document their progress, reporting on recent achievements and future challenges
FHMM analysis for Multi-Defect Spectroscopy in HfOX RRAM
No full textThis paper presents a new technique to analyze the characteristics of multi-level random telegraph noise (RTN) in HfOX RRAM. RTN is characterized by abrupt switching of either the current or the voltage between discrete values as a result of trapping/de-trapping activity while reading the RRAM cell. RTN statistical properties are deduced exploiting a factorial hidden Markov model (FHMM). The proposed method considers the measured multi-level RTN as a superposition of many two-levels RTN, each represented by a Markov chain and associated to a single trap, and it is used to retrieve the statistical properties of each chain. These properties (i.e. dwell times and amplitude) are directly related to physical properties of each tra
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