54 research outputs found
Property verification in the design of telecom applications
The industrial interest in the application of formal methods in the design of complex ASICs is noteworthy to improve the efficiency of the design process (reduced time-to-market) and to increase the quality of the final products (increased competitive profile). In this paper we focus our attention on design capture and functional verification, two critical phases in the current design methodologies. A modular toolset built around a model checker is described. A telecom co-processor is presented, and general properties derived. A user-oriented taxonomy of properties is introduced to support the design practice. Guidelines for the application of this technique are inferred from the example and generalize
Implicit Testability Techniques for VHDL Based ASIC Design
Implicit Testability Techniques for VHDL Based ASIC Desig
An Extended Testing Methodology for VHDL Based High-Level Design
An Extended Testing Methodology for VHDL Based High-Level Desig
The Request Testability Methodology for VHDL Based ASIC Design
The Request Testability Methodology for VHDL Based ASIC Desig
Research on different methods for the evaluation of the level of olive fruit-fly infestation. Results obtained in the experiments carried out in Tuscany in the biennium 1980-1981
Applicazione pratica dell'Hospital-based Hta: organizzazione di un Acute Chronic Pain Service al Policlinico San Matteo di Pavia
Towards WSI testable devices: an improved scan insertion technique
The aim of this paper is to introduce a different approach for the application of the partial scan methodology into a circuit to provide the most convenient solution in terms of overheads and performances. First testability analysis, based on new testability conditions, is performed to identify areas that are hard-to-test; then the partial scan technique is applied in a modified fashion only to the identified critical areas
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