1,721,015 research outputs found
Investigation of the Impact of BTI Aging Phenomenon on Analog Amplifiers
Full text linkCMOS technology scaling allows the design of even more complex system but, at the same time, introduces some reliability problems. In particular, aggressively scaled microelectronic technologies are affected by the Bias Temperature Instability (BTI) aging phenomenon that results in an increase of the absolute value of the transistor threshold voltage with aging time and a consequent reduction for the microelectronic circuit reliability. In this paper we estimate the performance degradation caused by BTI on an operational amplifier (OPAMP) in open loop configuration as well as on three other analog amplifiers based on OPAMPs. The results have shown that BTI can seriously impact the performance of the investigated circuits, and that such performance degradation worsens as operating temperature increases. We also briefly describe a possible low-cost monitoring scheme to detect the performance degradation of the OPAMPs caused by BTI. The effectiveness of our monitor has been validated by means of pre-layout electrical simulations, and the results have shown that it can be reliably used to evaluate the OPAMPs aging degradation
Novel low-cost aging sensor
No full textPerformance degradation of integrated circuits due to aging effects, such as Negative Bias Temperature Instability (NBTI), is becoming of great concern for current and future CMOS technology. Here we introduce an aging sensor able to detect such degradations in the combinational part of a critical data-path. It requires lower area than recently proposed alternative solutions, and a lower or comparable power consumption. © 2010 author/owner(s)
High speed and highly testable parallel two-rail code checker
No full textIn this article, we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is totally-self-checking or strongly code-disjoint with respect to a wide set of realistic faults. The proposed checker is also particularly suitable to implement embedded two-rail code checkers, as it only requires two input codewords for fault detection. Our checker can be employed to check the correct operation of a connected functional block using the two-rail code, to implement the output two-rail code checker of "normal" checkers for unordered codes, or to join together the error messages produced by various checkers (possibly using different codes) present within the same self-checking system. The behavior of our checker has been verified by means of electrical level simulations (performed using HSPICE), considering both nominal values and statistical variations of electrical parameters. © 2003 IEEE
Checkers' no-harm alarms and design approaches to tolerate Them
No full textIn this paper we analyze the probability that transient faults, multiple or single, affecting a checker of a self-checking circuit (with particular reference to the case of circuits using the two-rail code, the parity code, the Berger code and the Bose-Lin code) give rise to no-harm alarms, here defined as indications of errors neither denoting the presence of an incorrect word at the output of the functional block, nor denoting the presence of checker internal faults possibly compromising its ability to discriminate input codewords from input non-codewords. Differently from all other error indications, no-harm alarms could be conveniently ignored (or tolerated) by the system, with no need to adopt any recovery strategy upon their reception, otherwise for instance leading to exclude the self checking circuit from the whole system, or to degrade system's performance. A new property (No-Harm Alarm Robustness) is defined for checkers, allowing to discriminate "true" error indications from no-harm alarms. A possible approach to design checkers featuring such a property is proposed. The behavior of the derived checkers has been verified by means of electrical level simulations, and their costs are discussed. © 2007 Springer Science+Business Media, LLC
Low cost scheme for on-line clock skew compensation
No full textIn this paper we propose a novel buffer scheme that is able to compensate undesired skews between clocks of a synchronous system in a negligible time upon skew occurrence, thus being suitable also for on-line clock-skew correction. Clock signals are aligned one with respect to the other, starting from a reference clock, and moving forward among physically adjacent clock signals, thus creating no problem of reference clock's routing. Our solution is also able to compensate clock duty-cycle variations, which have been shown very likely in case of faults, for instance bridgings, affecting the clock distribution network. Compared to alternate solutions, our proposed scheme enables significant reductions in area overhead and power consumption, and is suitable for on-line compensation. Therefore, it allows clock skew and duty-cycle fault tolerance, thus increasing process yield and system's reliability. © 2005 IEEE
Novel high speed robust latch
No full textIn this paper we propose a new robust latch, referred to as HiPeR latch. It is insensitive to TFs affecting its internal and output nodes by design (independently of the size of its transistors), thus being scalable with technology node. It presents better or comparable robustness to TFs compared to the most recent latches in literature, while providing better characteristics in terms of performance at comparable area and power cost. © 2009 IEEE
Novel Transient Fault Hardened Static Latch
No full textIn this paper we analyze the effects of transient faults (TFs) affecting the internal nodes of conventional latch structures and we propose a new latch design which allows to tolerate such faults. In particular, we show that standard latches using back-to-back inverters for their positive feedback are very susceptible to glitches on their internal nodes. We propose a new latch that is hardened with respect to transient faults on the internal nodes and that provides lower power-delay product than classical implementations and alternate hardened solutions, while featuring a comparable or lower area overhead
Transient fault and soft error on-die monitoring scheme
No full textIn this paper we propose an on-die monitoring scheme to detect and count transient faults (TFs) resulting, as well as not resulting in output SEs, affecting the inputs of data-path latches/flip-flops. This approach allows an early monitoring of the latches/flip-flops vulnerability to TFs, thus discovering intrinsic weaknesses of design or process. The proposed monitoring scheme features a very low impact on area overhead and power consumption, thus being suitable to be deployed within any IC. © 2010 IEEE
Fast and low-cost clock deskew buffer
No full textWe propose a clock buffer that is able to compensate clock skews possibly due to process variations, and correct even more severe skews, as those possibly due to faults affecting the clock distribution network or those due to power supply noise. Compensation/correction is performed instantaneously, during system run-time, upon skew occurrence. Compared to alternative solutions which can be used to compensate/correct skews between couples of clocks, that presented here is definitely faster, features lower area overhead and power consumption, and does not require any initialization phase at the beginning of system operation. Additionally, our proposed buffer is also able to compensate/correct clock duty cycle variations due to process parameter variations, as well as faults affecting the clock distribution network. Also in this case, compensation/correction is accomplished within the same clock cycle of duty-cycle variation occurrence. © 2004 IEEE
Model for transient fault susceptibility of combinational circuits
No full textTransient faults (TFs) are increasingly affecting microelectronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional electrical level simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a new model to estimate accurately the possible propagation of transient fault-due glitches through a CMOS combinational circuit. We will show how the proposed model can be applied in order to estimate the TF susceptibility of a circuit by simply considering the propagation delay of the datapath. Therefore, the proposed model is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to electrical level simulation. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations
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