1,721,122 research outputs found
Automated Test Equipment for research on Non volatile memories
No full textThis paper presents a measurement system for research on nonvolatile
memories, such as Flash, EPROM, EEPROM. The instrument architecture is
based on the PCI local bus, thus allowing a direct interface of the memory
under test with the PC controlling the measurement. A rank of
programmable waveform generators allows applying arbitrary signals to
the memory cells during writing and reading, thus guaranteeing the
flexibility required at the research level. The instrument performances
have been evaluated on 4 MB test chips and results are comparable to
those of commercial Automated Test Equipment. This instrument,
besides the analysis of writing operations, can be successfully used
to evaluate the evolution of such operations during memory cycling and
their impact on long-term reliability
Quantum effects in accumulated MOS thin dielectric structures
No full textThe role of quantum effects, strongly modifying the physics of SiSiO2 interfaces in accumulated thin-oxide MOS structures, is reviewed and discussed. The main differences with respect to the classical case are analysed: in particular, it is shown that the semiconductor voltage drop and the oxide barrier height for Fowler-Nordheim tunnel injection are largely modified by the quantization of the accumulation layers. The dependence of the barrier height on the oxide field has a remarkable impact on the modelling of thin oxides: in particular, the Fowler-Nordheim current is shown to be correctly estimated only if quantum effects are correctly taken into account. © 1994
Space-Charge Limitations of Tunneling Resonances
No full textA simple explanation is presented for the large quantitative discrepancies between theory and experiments regarding the effects of tunneling resonances in suitably designed, double-barrier heterostructures. It is suggested that the main limitation is due to the maximum amount of charge that can be accomodated on the resonant level without taking it out of the resonance energy-alignment condition. As this is normally much less than that required for a fully developed resonance, the experimental effects are proportionally reduced. © 1986
Fast Identification of Critical Electrical Disturbs in Nonvolatile Memories
No full textWe propose a new methodology for a fast top-down identification of disturbs in large arrays of nonvolatile memories. The new strategy aims at providing the set of all the effective and dangerous disturbs present in a technology with no a priori selection of the physical mechanisms to be targeted. No simulations are needed, and neighbor-cell influence on disturb is empirically taken into account. This top-down strategy requires a limited set of experimental measurements and provides, in a fast "one-shot" approach, a complete disturb assessment, including the effects of new failure mechanisms. Experimental results on nonconventional floating gate Flash test chips are shown and discussed in order to demonstrate the features and the validity of the proposed methodology
Reliability in Wireless Systems
No full textThe objective of this chapter is twofold: from one side, techniques and methodologies of the failure science are introduced for each three development phases; on the other side, some practical examples of these methodologies are shown for the case of wireless systems.
During phase 1 the reliability of the entire system can be estimated in a general way thanks to failure analysis predictive tools based on failure probability data/models available for each system component (Reliability Predictive Modeling, RPM). The resulting model can be semi-empirical and, as such, it will be based on a huge amount of data. The Military Handbook is a standard example of this type of predictive methodology. Alternatively (or in addiction), it is possible to take into consideration the physical knowledge of the failure mechanisms that are always supposed to be present. The resulting models allow calculating the MTTF in a more accurate way as a function of some basic physical quantities involved in the failure mechanisms. The knowledge of both models is fundamental to address the first project phases and provides accurate estimates of the system reliability. In addition, the failure models allow selecting the methodologies, the criteria and the characteristic parameters for the accelerated tests performed during design and validation phases. Examples of instruments used during phase 1 and related to reliability prediction and modelling will be discussed in section 2 and will consider electronic devices such as MESFET and, semiconductor memories, and some physical mechanisms such as corrosion and ionic migration. The evaluation of the MTTF will also be addressed.
Phases 2 and 3 will be discussed in a more general way in sections 3 and 4, where the techniques used in these phases will be applied to a common mobile phone part: the vibrating motor. Issues related to phase 4 will be tackled in section 5 regarding the burn-in, the fault tolerance, the relationship between defects, yield and reliability and the use of redundancy in memories
Reliability of erasing operation in NOR-Flash memories
No full textThe erase operation in NOR-Flash memories intrinsically gives rise to a wide threshold voltage distribution causing various reliability issues: read margin reduction; increase of total bitline leakage current and electrical stress during reading and programming. This paper will address and review the erasing operation by analyzing the causes, the reliability issues and the possible solutions of the erased threshold voltage distribution width, the presence of ultrafast bits, the erratic erase phenomenon, the presence of a significant tail (extrinsic behavior) in the erased distribution and the intrinsic oxide degradation during cycling (oxide aging)
Impact of High Tunneling Electric Fields on Erasing Instabilities in NOR-Flash Memories
No full textExperimental data and analysis show that overerase effects in NOR Flash memories increase with the electric field used during erasing. We found that the electric field is an accelerating factor for cell degradation during cycling. Tunnel oxide degradation reaches a critical level above which the cell starts showing erased threshold voltage instabilities possibly leading to single bit failure. Experimental data show that cell degradation during erasing has to be ascribed to hole injection rather than to electron injection and that both hole trapping and detrapping increase with the electric field. The total stress time required to reach the critical degradation level has been found to follow a 1/Eox exponential dependence which is similar to the oxide breakdown phenomena thus establishing a physical link between the two phenomena. Anode Hole Injection has been suggested as hole generation and injection mechanism occurring during erasing and it is shown to be consistent with the experimental data
Characterization of the Over-Erase Algorithm in FN/FN embedded NOR Flash arrays
No full textThe over-erase algorithm is the state of the art procedure exploited in NOR Flash architectures to increase the memory reliability against the over-erase phenomenon mainly caused by either fast or erratic bits. In FN/FN architectures, since the soft-programming operation involved in the algorithm uses the same physical mechanism of the erase operation, its execution potentially triggers additional failures. In this paper, a detailed characterization of the soft-programming failures is provided by categorizing their statistical occurrence in order to capture their relationship with the failures exposed after the execution of the algorithm. A model of the failure rate is then derived to provide a rough guideline for over-erase algorithm optimization in terms of performance and reliability
Statistical Investigation of Anomalous Fast Erase Dynamics in Charge Trapping NAND Flash
No full textIn NAND Flash non-volatile memories the erase
operation drives the memory cells threshold voltage toward
negative values, barely representing a concern for Multi-Level
architectures. However, during the analysis of the erase dynamics
in Charge Trapping (CT) memory arrays using an Incremental
Step Pulse Erase algorithm, it has been found that a small
population of memory cells ( 2%) may randomly exhibit
anomalous fast erase dynamics which causes threshold voltage
fluctuations during cycling operations. The purpose of this letter
is to provide a statistical characterization of this phenomenon in
CT-NAND Flash arrays, thus helping the comprehension of its
underlying physical mechanisms
Erratic Erase in Flash Memories (part I): Basic Experimental and Statistical Characterization
No full textThis paper presents experimental results and statistics about the erratic erase in Flash Memories, setting the basis for any physical modeling of the phenomena and data comparison. Statistical parameters like the reliability function and the failure rate have been measured and modeled by analytical functions showing that all cells of an array may potentially exhibit erratic events. By mapping the physical position of each erratic bit in a sector and using an equivalent cell approach, it has been possible to establish a correlation between the erratic phenomena and the intrinsic amorphous nature of SiO2. Tail bits of the erased distribution have been shown to be caused by erratic events suggesting a unique physical cause for the two phenomena. The relation between positive and negative shifts has also been discussed and overerase risks caused by erratic behaviors have been estimated
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