1,721,261 research outputs found
25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process
No full textThe need for the high-speed analogue-to-digital converters demands the use of regenerative comparators. The strong positive feedback present in the regenerative comparators helps the comparator to work efficiently at the high-speed operations. This work proposes a low power auxiliary circuit to improve the high-frequency performance of the comparator. The proposed architecture along with the conventional comparators is simulated in 65-nm complementary metal oxide semiconductor (CMOS) technology with a supply voltage of 0.9 V. The maximum operating frequency of the proposed comparator is 6.25 GHz for a differential input voltage of 1 mV
Current Conveyor based Novel Gyrator filter for Biomedical Sensor Applications
No full textThis paper presents a lossy gyrator, which is used to implement a universal second order current mode filter. The proposed lossy gyrator uses conventional Second Generation Positive Current Conveyor (CCII) as a basic building block, which has -3 dB bandwidth of 230 MHz and a total power consumption of 15.31 mu mathbf{W}. A universal second order current mode filter is designed using proposed lossy gyrator, which achieves a high cutoff frequency of 18 Hz in low pass mode, a low cutoff frequency of 345 Hz for high pass, and a band pass response with resonating frequency at 90 Hz with a total power dissipation of 57 mu mathbf{W}. Simulation is done using standard 180 nm CMOS technology at ±0.5 V supply voltage
A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process
No full textThis paper proposes a dual ramp, pulse position modulation analog-to-digital converter. A delay cell is proposed in this work, which converts the timing information into a thermometric code. The proposed architecture uses a dual ramp, which initiates the time to digital quantization from both Most Significant Bit (MSB) and Least Significant Bit (LSB) ends. It requires the use of two current sources at both the ends resulting in more symmetrical non-linearity behavior compared to single-ramp architecture, thus improving the INL of the ADC. This technique leads to an increase in the sampling frequency by a factor of 2. It is designed and implemented in a 65-nm CMOS technology with a supply voltage of 1-V. The proposed ADC achieves an effective number of bits of 4.49 bits at a sampling rate of 100 MHz
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