103 research outputs found
Two-dimensional semiconductor alloys: Monolayer Mo1-xWxSe2
No full textMonolayer Mo1-xWxSe2 (x = 0, 0.14, 0.75, and 1) alloys were experimentally realized from synthesized crystals. Mo1-xWxSe2 monolayers are direct bandgap semiconductors displaying high luminescence and are stable in ambient. The bandgap values can be tuned by varying the W composition. Interestingly, the bandgap values do not scale linearly with composition. Such non-linearity is attributed to localization of conduction band minimum states around Mo d orbitals, whereas the valence band maximum states are uniformly distributed among W and Mo d orbitals. Results introduce monolayer Mo1-xWxSe2 alloys with different gap values, and open a venue for broadening the materials library and applications of two-dimensional semiconductors
Tuning Interlayer Coupling in Large-Area Heterostructures with CVD-Grown MoS2 and WS2 Monolayers
No full textBand offsets between different monolayer transition metal dichalcogenides are expected to efficiently separate charge carriers or rectify charge flow, offering a mechanism for designing atomically thin devices and probing exotic two-dimensional physics. However, developing such large-area heterostructures has been hampered by challenges in synthesis of monolayers and effectively coupling neighboring layers. Here, we demonstrate large-area (>tens of micrometers) heterostructures of CVD-grown WS2, and MoS2 monolayers, where the interlayer interaction is externally tuned from noncoupling to strong coupling. Following this trend, the luminescence spectrum of the heterostructures evolves from an additive line profile where each layer contributes independently to a new profile that is dictated by charge transfer and band normalization between the WS2 and MoS2 layers. These results and findings open up venues to creating new material systems with rich functionalities and novel physical effects
Ensuring The Homogeneity OF Spray Pyrolised SnS Thin Films Employing XPS Depth Profiling
No full textSnS thin films were prepared using chemical spray pyrolysis (CSP) technique. p-type SnS films with direct band gap of 1.33 eV and having very high absorption coefficient were obtained with the optimized deposition conditions. In this paper we focus on investigating the uniformity and phase purity of the hence deposited SnS films employing Raman and X-ray Photoelectron Spectroscopy (XPS) analysis. Raman Spectra of the films had only single peak corresponding to the Raman active Ag mode at 224 cm(-1) which is characteristic for phase-pure SnS thin films. Detailed XPS analysis on these samples were performed by scanning the peaks for Sn, S, and O with high resolution to estimate the chemical states and composition. Employing Ar-ion sputtering, the depth profiles showing variation in concentration and binding energies of S, Sn, O over the sample thickness were obtained and the uniformity in composition along the thickness has been discussed in detail
Where AES is for Internet, SIMON could be for IoT
No full textAbstractWith the upcoming era of Internet of Things and the Pervasive Computing, there is a need to develop block ciphers with tight constraints such as area, power, memory, performance, throughput and others. These are so called the lightweight block ciphers which are specifically intended for resource constrained platforms. Lined up in the line is SIMON, a light weight block cipher proposed by NSA after the prompting from the U.S. Government in the year 2013 along with SPECK lightweight block cipher. SIMON implementation on hardware has excellent results in terms of area and has been found to be a very strong alternative to the existing AES. This paper involves the basic design considerations, round functions, key schedule and parameters of SIMON and also we can look forward into the implementations of SIMON in hardware comparing with the existing AES standard. This paper also focuses on the analysis in terms of area, power and delay of the SIMON 64/128 configuration in Cadence Synthesis RTL Compiler using the CMOS 180 nm and 90 nm technology libraries
An Implementation of Modified Lightweight Advanced Encryption Standard in FPGA
No full textAbstractAdvanced Encryption Standard (AES) is the standardized block cipher, which is used in various applications. AES is well suited for software and hardware implementation with versions of 128,192,256 key sizes. In hardware implementation AES is advantageous as it is more secure, low cost, and has minimized hardware utilization. Lightweight block ciphers are developed for the efficient implementation in hardware. An approach to design a technique to implement AES as lightweight block cipher is an immediate requirement of the time. An approach, to make AES a lightweight block cipher, is being discussed such that designing the steps of AES such as mix columns, substitute byte in AES is to be implemented in a parallel manner. The latency in this implementation is considered to be less comparing the conventional implementation of AES. The conventional and the new approach are to be simulated in XILINX 14.2 and is being compared in the aspects of area and latency. The design is to be implemented in FPGA
Studies on Red Pigment and Statin from Native and Fermented Medicinal Rice-Njavara
No full textThis Dissertation / Report is the outcome of investigation carried out by the creator(s) / author(s) at the department/division of Central Food Technological Research Institute (CFTRI), Mysore mentioned below in this page
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